new project feesability

[davidp]

I work with three phase power and i have a need to do take readings, do math, and output a result on all three phases at the same time, (in parallel).

Questions i have
What is the clock frequency of a single core?
Can many cores read a memory location or variable that one core is generating?
are there any DSP instructions for PID or PI controllers?

[mon2]

Hi davidp.

What is the clock frequency of a single core?

Clock frequency for the CPU is 400 to 500 Mhz and varies with the CPU device being selected. The MIPS per logical core value will vary with the number of active cores. This value can be 100 to 125 Mhz as the peak value or as low as 62.5 Mips.

Take for example P/N XS1-L4A-64-TQ4 which features 4 cores. The datasheet shows this device can be clocked at 400 Mhz and each of the 4 cores can support 100 MIPS operation. From the datasheet:

There is no way that the performance of a logical core can be reduced below these predicted levels.

Moving on to say P/N XS1-L16A-128-FB324. This device has 2 tiles (just consider them as 2 CPUs in a single package). Each tile (aka CPU) is able to support 8 cores (threads) of parallel operation. You do not have to use this many and will benefit on the MIPS per core value if you do not as follows:

< see page 10 of the datasheet as this editor is horrible for adding graphics >
https://www.xmos.com/support/silicon/da ... 9&secure=1

The more cores that are active, the lower the MIPS value will be but the MIPS value is predictable.


Can many cores read a memory location or variable that one core is generating?

Yes. Here are some discussions on this topic:

https://www.xcore.com/forum/viewtopic.php?f=26&t=1550

https://www.xcore.com/forum/viewtopic.php?f=26&t=3061

https://www.xmos.com/support/tools/prog ... 53&page=22

Given that each core is running in parallel, you could also broadcast / send the contents of the memory location / variable to another core very quickly. Quick enough that for your project, there will be no issue. However with the methods above, you access the same common memory location across cores.

are there any DSP instructions for PID or PI controllers?

http://www.xmos.com/products/why/dsp

https://github.com/xcore/sc_dsp_filters

https://github.com/xcore/sc_dsp_transforms

https://github.com/xcore/ap_par_audio_dsp

http://www.xmos.com/support/appnotes/AN01011

http://www.xmos.com/published/dsp-audio ... on-library

https://www.xmos.com/support/xkits?subc ... 825&page=1

http://www.xmos.com/support/appnotes?su ... 20examples

The CPUs can interconnect with each other and offer very low latency communication between the physical CPUs so you can create a cluster of XMOS CPUs as many as you need to expand your project's needs. An article was recently posted on this subject on how to apply with and without LVDS transceivers.

See here:
http://www.xmos.com/support/appnotes/AN01024

[srinie]

Hi Kumar,
Excellent consolidation of all relevant resources under a single place.

Thanks.