Quick question. In AN00203 the tdm_config.offset value seems to be set to -1 (main.xc line 114). However, the API (i2s.h line 31) says this value is to be from 0 to 31... what am I missing?
This offset is the number of BCLK cycles the FSYNC goes high before the MSB of the first data word in the frame. The resulting code for FSYNC generation doesn't make sense to me when offset is -1.
AN00203 tdm_config.offset
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akp
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Ross
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That looks like bad info/description relating to the TDM implementation - please could you add an issue here: https://github.com/xmos/lib_i2s
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akp
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Done, thanks.