Custom board with L16 -> U8 errors

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pgbross
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Custom board with L16 -> U8 errors

Post by pgbross »

Hello,

I have a custom board using an xs1 L16A-128-QF124 connected to a U8A-64-FB96 part, but it won't boot with both parts in the JTag chain. If I remove the U8A part from the chain, then the board will boot and run code using an XTag2 and the xrun --io <executable.xe> command.

With just the L16 part in the JTag chain, then xrun -l gives the following result:

Code: Select all

0     XMOS XTAG-2             iFQVO9dv        L[0..1]
but with the U8 part in the chain I get this:

Code: Select all

0     XMOS XTAG-2             iFQVO9dv        ??G[1]->L[2]
where it is misidentifying the devices.

The L16 part has the X1LA xConnect link connected to the U8 parts X0LB with the expectation that once we have the board functioning the L16 part will boot its first node from SPI, and its second node and the U part from a link.

Whenever I try running a simple program, such as a one line print 'hello world' the error message is
xrun: First stage multi-node boot failed, please check XN file and Xmos link connectivity
.

My hardware designer has been over the board and cannot find an issue as is frustrated as it appears to be working as intended, other than it won't boot. The various resets and JTag data is appearing at the XSYS header, so the JTag chain appears correct. There is however no sign of any activity on any of the xCONNECT links. This is happening on three separate boards with identical behaviour so it feels like a hardware fault, but is tricky to understand. My previous experience is only with the G4 part, and this is my first multichip board, so am not sure where the fault may be.

Has anyone successfully chained a U8A part from an L16 part (particularly from the second node of the L16 part)? I have seen posts about the Multi function audio reference design, which I believe uses the U8A part, chaining to a sliceKIT L16, but that is the other way round (by necessity as the MFA board doesn't itself have a chain connector).

thanks,
Philip

p.s. I am using the 13.0.2 version of the tools in case that is relevant.


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segher
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Post by segher »

Hi Philip,

Could you post the relevant parts of your schematic? Everything
JTAG, MODE pins, RESET, maybe clocks too.

You have checked whether your supply voltages are good and
stable, I assume ;-)
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mon2
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Post by mon2 »

Hi Philip. You are slightly ahead of us as we too have been working on this topic for the past 2 weeks. Our first project will mate 2 of the L16A (124 pin) devices with the Master booting from SPI flash and the Slave is to boot through XLINKs. Next generation will expand to include more similar devices. After much reading and some dialog with XMOS (USA), please note our following comments:

(courtesy of Mark Seel of XMOS, USA)

This should help you understand how your two parts are connected together, are connected to the XSYS header, and what GPIO's you have left over for your application specifics.

Device #1
FLASH: Pins X0D00, X0D01, X0D10, X0D11 connected to FLASH part
XTAG: Signals TMS, TCK, DEBUG_N, RST_N/TRST_N connected to XSYS header
XTAG: Signal TDI connected to XSYS header,
XTAG: TDO connected to TDI of next device in chain (Device #2)
XTAG: Signals XLB0in, XLB1in, XLB0out, XLB1out connected to XSYS header (for XSCOPE)
MODE: MODE[2] and MODE[3] connected to XSYS pin 3 (MSEL) to boot via JTAG or SPI
xConnect: XLA connected to XLB on Device #2

Device #2
XTAG: Signals TMS, TCK, DEBUG_N, RST_N/TRST_N connected to XSYS header
XTAG: Signal TDI connected to TDO of previous device in chain (Device #1)
XTAG: Signal TDO connected to XSYS header
MODE: MODE[2] grounded and MODE[3] connected to XSYS pin 3 (MSEL) to boot via JTAG or XLB
xConnect: XLB connected to XLA on Device #1


We would like to add these comments / suggestions:

a) width of your xCONNECT links is 2 or 5 wire ?
b) how far apart are the 2 XMOS devices ?
c) if the distance is relatively short - do you have the recommended 33 ohm resistors in series for the xCONNECT links near the transmitters ? (else recommended lvds transceivers must be applied)
d) are there the recommended pull-downs on the xCONNECT links (10k) ?
e) as per section F of the datasheet, with multiple XMOS devices, you may be required to apply buffers onto the XTAG interface to properly drive each. We applied open drain buffers.
f) As per Segher, how is your power sequencing ? Ample current for 2 devices ?

We have not yet reviewed on how to inform the master XMOS controller to make use of the specific xCONNECT links so cannot comment on your choice of X1LA (vs X0LA).
pgbross
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Post by pgbross »

Hi,
Thanks for the comments so far. Here is a trace of the power supply sequencing showing, in particular, the 1v05 core voltage doesn't get applied until the 3v3 supply is stable.
psu_trace.png
Power supply sequencing
(111.86 KiB) Not downloaded yet
psu_trace.png
Power supply sequencing
(111.86 KiB) Not downloaded yet
On the other questions:
a) the connection is 5wire.
b) the L16 and U8 devices are approx. 20mm apart.
c) the xCONNECT link between the L16 part and the U8 part is about 30mm of pcb trace and has 33r resistors close to the transmitters.
d) there are no pull downs on the xCONNECT links - do you have a reference for this requirement?
e) the XTAG interface has a 74c08 buffering the signals for driving the signals strongly enough for two chips.
f) see attached psu trace.

Segher, there are some mods that have been made to the pcb to correct some errors in the original prototyping, and I haven't got a version of the schematic from the hardware designer updated to reflect those changes yet. If I can get an updated version I will post the relevant sections here shortly, otherwise I will use the schematic I have and add annotations as to what differs.

In the meantime we are modifying the pcb to allow the U8 part to be the only device in the JTag chain, to ensure that we are really looking at an interconnect issue and that there is not an underlying problem we have missed. This involves cutting a couple of tracks as the pcb layout did not anticipate needing to isolate the devices even for the prototype.

I will post back with the results in a few days when the hardware changes are made and we can run some tests.

thank,
--Philip.
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segher
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Post by segher »

Hello again,
pgbross wrote:Here is a trace of the power supply sequencing showing, in particular, the 1v05 core voltage doesn't get applied until the 3v3 supply is stable.
The sequencing is fine. It looks very noisy but that is probably
just your measurement.
c) the xCONNECT link between the L16 part and the U8 part is about 30mm of pcb trace and has 33r resistors close to the transmitters.
d) there are no pull downs on the xCONNECT links - do you have a reference for this requirement
Pulldowns are not a requirement; you need them if the board
is too noisy, and much more likely if you have long lines. You
would put them on if when the transmit side is not enabled yet
the receive side could see a signal -- it won't usually happen.
You can often do without the inline 33R as well, saving a tiny
little space and money, but good luck reworking _that_ when
you need it ;-)
There is a doc just about xlinks, it describes these things, let
me know if you cannot find it.
e) the XTAG interface has a 74c08 buffering the signals for driving the signals strongly enough for two chips.
Buffering which signals, exactly? Not all are the same. Well
we'll see on the schematic.
otherwise I will use the schematic I have and add annotations as to what differs.
That is fine; either way is much more efficient than guessing games
and pulling teeth :-)
In the meantime we are modifying the pcb to allow the U8 part to be the only device in the JTag chain, to ensure that we are really looking at an interconnect issue and that there is not an underlying problem we have missed.
I would first look at why your JTAG isn't working; you need it
for debugging anyhow, you won't get far without it; and it
not working means there might be something seriously wrong.
This involves cutting a couple of tracks as the pcb layout did not anticipate needing to isolate the devices even for the prototype.
A single jumper (or mux) in TDO/TDI should do the trick. You might
have to tell xrun to drive the JTAG slower.

Good luck, have fun,

Segher
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segher
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Post by segher »

4.4 in this doc has the info on resistors for the xlinks.
That's not the doc I meant though. Oh well.
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segher
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Post by segher »

7408... That's a NAND. Some open drain buffer would be
simpler probably. Which exact device family? Some do not
drive strongly enough.
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mon2
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Post by mon2 »

What are your MODE pin strappings for the U8A-64-FB96 part ?
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XMatt
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Post by XMatt »

pgbross wrote:Hello,

I have a custom board using an xs1 L16A-128-QF124 connected to a U8A-64-FB96 part, but it won't boot with both parts in the JTag chain. If I remove the U8A part from the chain, then the board will boot and run code using an XTag2 and the xrun --io <executable.xe> command.

With just the L16 part in the JTag chain, then xrun -l gives the following result:

Code: Select all

0     XMOS XTAG-2             iFQVO9dv        L[0..1]
but with the U8 part in the chain I get this:

Code: Select all

0     XMOS XTAG-2             iFQVO9dv        ??G[1]->L[2]
where it is misidentifying the devices.

The L16 part has the X1LA xConnect link connected to the U8 parts X0LB with the expectation that once we have the board functioning the L16 part will boot its first node from SPI, and its second node and the U part from a link.

Whenever I try running a simple program, such as a one line print 'hello world' the error message is
xrun: First stage multi-node boot failed, please check XN file and Xmos link connectivity
.

My hardware designer has been over the board and cannot find an issue as is frustrated as it appears to be working as intended, other than it won't boot. The various resets and JTag data is appearing at the XSYS header, so the JTag chain appears correct. There is however no sign of any activity on any of the xCONNECT links. This is happening on three separate boards with identical behaviour so it feels like a hardware fault, but is tricky to understand. My previous experience is only with the G4 part, and this is my first multichip board, so am not sure where the fault may be.

Has anyone successfully chained a U8A part from an L16 part (particularly from the second node of the L16 part)? I have seen posts about the Multi function audio reference design, which I believe uses the U8A part, chaining to a sliceKIT L16, but that is the other way round (by necessity as the MFA board doesn't itself have a chain connector).

thanks,
Philip

p.s. I am using the 13.0.2 version of the tools in case that is relevant.
Apologies this is a tools bug which has been found recently by another customer and fixed. I will supply a patch for you ASAP to fix the issue as an official release resolving this is a few weeks away.

Could you let me know what OS you are running the tools on so I an give you the correct file.
pgbross
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Post by pgbross »

Hi XMatt,

I am running the tools on Windows 8.1 64bit.

Also for information, I have had an update last night from my hardware designer, and when we isolate the U8A part's JTag chain it boots and runs normally, so the basic hardware seems to be functional and looking forward to getting a patch!

--Philip.
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