Reference Designs with 13MHz clock @ 500MHz PLL Settings

[bearcat]

I was looking at the PLL settings in detail, to determine if the PLL are an issue with booting my project.

I have the standard 13MHz clock for the USB tile, and USB ULPI transceiver. The reference code uses 500MHz for the tile frequency in the XN file, which I simply copied into my XN file.

But, looking at the PLL values that are used at these frequencies, left me confused. I pulled the actual register values using the debugger to verify that the PLL settings are the actual used, and they are.

So... Here's the bit fields:

PLLSettings.JPG

The PLL register was 0x3E70C at these frequencies. This gives:
R = 12
F = 999
OD = 0

Wow! The PLL is multiplying by a large 500X, with a pre-divider of 13.
Calculation: (999+1)/2 * (13MHz / (12+1)) = 500MHz

I can't image that large a multiplier is good. It has to add significant jitter and phase noise. Although it is a round number.

I changed to 500.5MHz, instead. This gives:
R = 0
F = 76
OD = 0

Only a 38.5X multipler.

It appears booting is better on my project, but still an issue.

Comments?????

[segher]

You decoded all that correct as far as I see.

The VCO output in the first case is 1GHz, which then is
divided by 1000; the input clock is divided by 13; both
become 1MHz signals which are then brought in synch,
which will take a while yes. After it has locked it shouldn't
jitter much, if your input clock is stable enough; and does
it matter anyway?

[bearcat]

I am not a PLL expert, so any comments are welcome if this is a concern or not. But the default configurations are optimized for the lowest F value given the frequency range specified. I believe PLL's are usually specified to a certain range for best performance.

Regarding my project, booting is different with the modified PLL values. One other thing, I didn't mention yet, is there appears to be a temperature effect.

[segher]

But the default configurations are optimized for the lowest F value given the frequency range specified.

What default configurations do you mean? The boot
configurations all give (almost) exactly 400MHz, with various
input clocks; if you mean the configs created from your XN,
those always try to match exactly the frequency you specify
(and then there is almost no choice left).

I believe PLL's are usually specified to a certain range for best performance.

Unfortunately we have no such documentation :-(

Regarding my project, booting is different with the modified PLL values.

Different? Faster? Something else?

One other thing, I didn't mention yet, is there appears to be a temperature effect.

Are you sure you are not imagining that? The PLL uses at
most 7mA.

[bearcat]

The PLL setting default via the mode pins have a F maximum of 125, I believe. The pre-divider has 2 as a maximum.

I am going to hook a scope up and see what the jitter is for the two different settings. For my own curiosity. I expect to see a difference.

This is a continuation of my quest to get my 10 tile board to boot reliably. I discovered last week that when I put my project in an enclosure, and let it heat up 10-20 degrees F it wasn't booting after it warmed up. The project runs and runs the application without error, warm, cool, or hot after it boots.

For booting, there is a difference with the PLL. I am using a Microchip as the board supervisor that has control of power and reset. So I can program anything I want.

PLL @ 500.0MHz
Cool: Boot first time 95% of the time.
Warm: Doesn't boot. Reset taps, nor power down->up work. 3 Minute cool down, works.

PLL @ 500.5MHz
Cool: Never boots first time, after a second reset tap, usually always boots.
Warm: I can usually get it to boot after a few reset taps, or power cycle second reset tap without any cool down.

I am not trying to say any of the above sequence is important, and certainly NOT a solution, nor is it definitive. Just observations. I am observing that some timing changes with temperature.

Basically there are improper timing constraints in the boot code. The reference designs build from each other, so the designs tend to be the same and I suspect most of the testing was done with the reference designs. In a single Tile system, PLL lock and timings are less an issue.

Thanks for any comments.

[mmar]

Your issues maybe isnt PLL , but power sources order start.
Try controll 3.3V vs 1V starting cool and warm sequence.

[segher]

Yes, all boot modes use small divider settings. That is simply
because all frequencies involved are nice round numbers --
except for the 13MHz/399.75MHz case. Would be interesting
to hear why that was chosen.

I'd love to see your jitter measurement results.

Temperature... I thought you were saying the chip heats up
more with certain PLL settings, but you are saying things behave
differently (larger lock time?) at different temperatures. Not
really unexpected, but one more variable to take into account :-(

Strange that the 500.5 never boots the first time.

I still see only two solutions to your problems: either you get
fixed boot code from XMOS, or you don't use that boot code
(either write your own, or boot the nodes separately).

[bearcat]

Measuring jitter is not easy. These measurements are only a quick indicator.

I configured a port to output a 50MHz clock. Two tests, using both of the PLL settings. My scope is only 50MHz, so the signals are not very digital. I set scope to have 50% infinite persistance.

It appears that the jitter performance is similiar using either a 38.5X, or 500X. Maybe 500.5MHz is very slightly better. Interesting...

Here's 500MHz:

V5 50Mhz Output Clock Jitter PLL 500Mhz.JPG

Here's 500.5MHz:

V5 50Mhz Output Clock Jitter PLL 500.5Mhz.JPG

Here's an 500MHz FFT (which doesn't show anything more):

V5 50Mhz Output Clock Jitter PLL 500Mhz FFT.JPG

[bearcat]

Power supply sequencing has been verified. The 1V rail starts 2mS after the 3.3V. You have to use two graphs to compare, but are included below.

The boot process actually blocks after the stage 1 loader has executed, so the tiles are actually running code.

Here's 1V vs 5V:

V5 5V vs 1V with 10K.JPG

Here's 3.3V vs 5V:

V5 5V vs 3.3V.JPG

[bearcat]

Any code available as a starting point for a boot loader? That sounds like alot of work.

Did any changes get made in V13 final regarding boot loading? I tried V13 beta1 without success, but not V13 final yet. I didn't notice any specific notes in the changes log.

Thanks for all the replies.