SliceKit with SDRAM slice card

[octal]

Hello,
did anyone tested the effective bandwidth achievable with this slice card? the doc advertise something like 70MByte in burst write mode. How is this achievable? by writing 8 or 16bit values? if 16bit values, that means that max data transfer between any core and the SDRAM server core is limited to about 35Mbytes if using 8 bit transactions? is that correct?

PS. please, any feedback (even unrelated to the question) about this card is welcome, as I'm planning to buy the whole SliceKit mainly for using SDRAM.

[Berni]

I would assume its 33.3MHz since thats about the fastest speed you can bit bang stuff at on a regular 400MHz chip.

Just keep in mind that SDRAM is a bit annoying in that you have to give it refresh commands every few milliseconds or you lose the data in it, if possible its a good idea to use a SRAM.

[octal]

Hi Berni,
some SDRAMs have autorefresh capabilities. The main choice of SDRAM instead of SRAM (which I'm using now) is the price. When trying to find quick access SRAM/SDRAM, the price for SRAMs (for 10ns for example) is arround 8 euros for 512KBytes, while 4 or more times capacity SDRAM (8MBytes) are arround 2 euros :(
this is why I'm looking at SDRAM alternative, which is used extensively with FPGA/CPLD, but seem noone on this forum is using it in production environment using XMOS chips.

[Berni]

Well auto-refresh just means that you send it a single command and it refreshes an entire page on its own, still need to manually send that command every so often for each page. There is a kind of SDRAM that does all of it automatically called PSRAM, but its still not going to be as cheep as that im guessing.

I remember seeing a project on XMOS that used external SDRAM for something, so it probably works fine. Meaby you want to just go ahed and spin your board since the slicekit does cost quite a bit and you have to include the cost of the SDRAM slice.

[androider]

Hello,
did anyone tested the effective bandwidth achievable with this slice card? the doc advertise something like 70MByte in burst write mode. How is this achievable? by writing 8 or 16bit values? if 16bit values, that means that max data transfer between any core and the SDRAM server core is limited to about 35Mbytes if using 8 bit transactions? is that correct?

PS. please, any feedback (even unrelated to the question) about this card is welcome, as I'm planning to buy the whole SliceKit mainly for using SDRAM.

Here are the numbers I got running the SDRAM benchmark:

Cores active: 8
Max write: 63.06 MB/s
Max read : 60.30 MB/s
Min Latency: 284.20
Max Latency: 323.21

Cores active: 7
Max write: 64.29 MB/s
Max read : 61.50 MB/s
Min Latency: 267.98
Max Latency: 301.01

Cores active: 6
Max write: 65.26 MB/s
Max read : 63.07 MB/s
Min Latency: 254.00
Max Latency: 283.54

Cores active: 5
Max write: 66.08 MB/s
Max read : 64.04 MB/s
Min Latency: 240.00
Max Latency: 272.55


Cores active: 4
Max write: 66.47 MB/s
Max read : 64.08 MB/s
Min Latency: 234.00
Max Latency: 271.10