Increasing channel count with DJ kit

[jjlm98]

Hi all,

I'd like to increase the number of channels from 4-in/4-out to 8-in/8-out on a design based on the DJ reference design, if possible. However, I find I am running out of single-bit ports to add PORT_I2S_ADC2, PORT_I2S_ADC3, PORT_I2S_DAC2, and PORT_I2S_DAC3 on my single-tile device. Since S/PDIF and MIDI are not used on my design, I can easily get back XS1_PORT_1B and XS1_PORT_1F which were previously mapped to PORT_SPDIF_OUT and PORT_MIDI_IN, respectively. With that in mind:

1. I operate the XCore in slave mode, so there is no need for an incoming MCLK_IN from which to divide down the I2S clocks. Can anyone offer advice as to how to remove this logic so that the compiler no longer seeks a definition for PORT_MCLK_IN (freeing up XS1_PORT_1E)?

2. Can the 8-bit port servicing PORT_MIDI_OUT (8D) somehow be mapped to the final single-bit port I need for the last I2S data line?

I should also note that I do not need any of the GPIO serviced by XS1_PORT_4C. I do need to keep the I2S lines mapped to XS1_PORT_4D.

If there's a better way to go about this problem, I'm certainly interested as well. Thanks in advance.

[larry]

Master clock is used for generating the high precision clock feedback to the USB host. It is also used to derive audio clocks in I2S master mode. So it can be shared by two cores like this, the corresponding master clock port is first attached to a clock block, and other ports clocked off this clock block. That restricts the master clock port to 1bit width.

The ports of the bit clock, word clock and data also need to be 1bit ports, as they are all operating in 1-to-32 ser-des mode.

This means the minimum 1bit port requirement for 8in/8out audio channels is 11. With the 9 available 1bit ports, the DJ kit could support 6in/6out.

[babazaroni]

How about using TDM?

[jjlm98]

Hi Larry - thanks so much for your comprehensive response.

Perhaps I misunderstood, but I was lead to believe from Ross's response to this thread that the DJ kit could be expanded to at least 10-in/10-out. If that's the case, can the implementation be modified to support more than 6-in/6-out?

Regarding babazaroni's point - what is the outlook for TDM being a supported option?

[infiniteimprobability]

Perhaps I misunderstood, but I was lead to believe from Ross's response to this thread that the DJ kit could be expanded to at least 10-in/10-out. If that's the case, can the implementation be modified to support more than 6-in/6-out?

Ross is right from a bandwidth point of view - that's what a single ISO endpoint can manage (192KHz * 32b * 10 = 61Mbps). However, that's the host side of the story.
You also need to get the audio off chip to the DAC/ADC and that requires ports. The single tile devices (e.g.. U8 used on DJ kit) have absolute max 9 1b I/O, so with mclk, bclk & lrclk as required, you have 6 lines left for I2S data. That's 12 ch total (or 6 in 6 out if symmetric).

Regarding babazaroni's point - what is the outlook for TDM being a supported option?

There are some experimental TDM implementations which are working but have not been tested thoroughly - however there is no standard so it's difficult to have a universal solution. It's certainly possible on XMOS.

[Ross]

Perhaps I misunderstood, but I was lead to believe from Ross's response to this thread that the DJ kit could be expanded to at least 10-in/10-out.

Sorry that wasn't my intention, I was meaning the reference design software in general.

[babazaroni]

jjim98, sounds like you are currently in the position I was a few months ago. The reference designs are fairly configurable, but as soon as you step outside it's bounds, you need to dive deeply into into how the ports work and become an expert. My design uses both I2S and TDM to get 10in and 12out channels. I prototyped it on startkit using the development kits from the codec suppliers and am in the process now of layout for the U6. Contact me for more info via babazaroni near gmail. Replace near with the obvious.

[infiniteimprobability]

It's great to see community members helping each other out - that's really in the spirit of this site.

Another solution at least worth considering is looking at a larger device. All chips have resource constraints - by moving up to say, an XS1-U8A-128-FB217-C10, you get a huge number of I/O and there is no need to worry about adding hardware muxing 1b ports, for example the SPI boot flash port.

Of course there is a tradeoff - it will cost more.. about 25% according to digikey
http://www.digikey.com/product-search/e ... ds=xs1-u8a
For that you get double the MIPS and up to 25 x 1b ports too..

For the increased component cost, it may pay off in terms of board complexity and your engineering time. There can also be further benefits if the spare MIPS you get and the extra I/O let you integrate other stuff from the board, such as a control MCU.

Of course each project will have it's own BOM cost vs development cost constraints so the value of this tradeoff is case by case.

[jjlm98]

Thanks guys for the comprehensive responses and ideas. Unfortunately, at this time, moving up to a 128-pin package isn't an option since our boards are back. As an interim solution, I've been delivering a handful of custom builds (4-in/8-out, 6-in/6-out, 8-in/4-out) to our teams in house as needed, to stay within the 12-channel limit.

What's the word on the TDM version? In my design, the 12 I2S channels actually interface to an FPGA, which itself is driving out various custom formats to a customer board. Whether the interface between the XMOS device and the FPGA consists of multiple stereo pairs in parallel, or a TDM stream (of any frame format) really makes no difference and is just a matter of modifying the RTL so long as the XMOS device can remain as a slave.