XS1 GPIO output stage
Posted: Fri Aug 22, 2014 1:22 am
Hi, i would like to know what the output/input stage looks like for ports on xmos chips (open-drain, push-pull, etc.). The datasheet only says there is a 35k pull-down resistor, but not very specific on how the data is driven on pins. Since there is already a pull-down i would maybe think there is an open-drain configuration for driving the high level, but really i just dont know. Is there an explanation and schematics of XS1 ports at transistor level? Most stuff seems to cover only how to interact with port registers from programmatic view.
I need a better understanding of this since i want to interface with some 1.2 V logic by using a voltage shifter.
Thank you!
I need a better understanding of this since i want to interface with some 1.2 V logic by using a voltage shifter.
Thank you!