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xcore.com update893Jan 18 '17 at 12:07

by henk916

Switch RX SPDIF input port on the fly #2111Jan 18 '17 at 17:03

by ffomich493

USB 2 CV Failed: Illegal FS bulk endpoint MaxPacketSize: 200124Jan 18 '17 at 17:02

by larry935

Define SELF_POWERED in run-time05Jan 18 '17 at 16:42

by kasemann31

XMOS for USB audio interface + audio app456Jan 18 '17 at 11:52

by adamski27

myif not used in two parallel statements (byte range 4..8)220Jan 18 '17 at 9:45

by aclassifier896

32x32 at 96k73942Jan 17 '17 at 17:09

by Ross2819

Can i use a RMII interface PHY with RGMII block?4702Jan 17 '17 at 10:04

by henk916

Interfacing startKIT to 5V238Jan 16 '17 at 13:03

by Ian15

xTIMEcomposer 14.2.4 on macOS 10.12 Sierra?045Jan 15 '17 at 23:24

by aclassifier896

Projects

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I need some help for connecting the  JTAG for a chained XMOS XS-LSA-128 Please check the attached schematic whether the connectinons and the logic will work for the chained XMOS XS_LSA-128 I cant get a stable start-up function in the e...
How can I use a 4bit port for the data out for an I2S master Tx, the Bclk, LRClk and Mclk are on single ports. I have run out of single bit ports and this seems to be the logical choice. I thought this would be the default for the TX data lines.
Dear XMOS folks, being a newbie on XMOS I want to understand how to transfer audio data (to write the code) from a while(1) loop that reads I2S data to another thread (while(1) loop) that sends the I2S data. (24bits, Wclk = 64 BitClks) The characteri...
cpld slice
Reconfigurable xmos slice extender. The goal of this project to design a slice extender board, which contains non-volatile reprogrammable cpld to connect io lines as required. The configuration can be written in verilog or similar vhdl laguage, and a...
The goal of this project is to create a low cost and simplified XCore-200 development board using KiCad. Since I'm a fan of open source (and commercial EDAs like Altium are ludicrously expensive) I decided to use KiCad. I started this project aro...
oogely boogely
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