High Speed data collection (DAC and ADC)

Amongst the many front~end processes the FFT is definitely a major.
I'm curious what kind of performance an Xcore can do in real-time.
If one where to need more multi~accumulates what do you think might be
a reasonable solution via cost/power. gals, fpga, sdr, forth-bots perhaps.
there are some fairly power conscientious pgpu's with in ARM. Sheeze!,
I don't know? I just keep getting that image of the robot~arm on the SAIL
computer from that movie "Demon Seed". Nickolas Wirth's Oberon runs on
ARM and is its OS, I think that it could serve and cross-compile STL C++
Binaries and hyper-visor your SYS-V, BSD, POSIX, LINUX blobages

For graphic's a Fast~Xlinked to SLI pgpu is going to have a power appetite.
The programmable abstraction likes FORTRAN good at math types. I wonder
what's new in the L2 as it relates to DSP functionality.
Is it just macros or is it in the hardware?
I'll see ; )

Because of link compatibility issues, I am designing around the L1 series. I am almost done with a 3 core design with ethernet on 1 core, SDRAM on another, and a couple Analog Devices 16 bit 1Msps pulsar ADCs. The ADCs are configured to receive 0-5V in differentially referenced to gnd via an AD8130 diff amp. I would have preferred the G4, but my system design is around L1 links. I will post my latest schematic when it is done. It has some extra baggage from a legacy design, so there are 32 bids of digital IO also.

I suspect that for a general purpose platform, especially if using the G4 bga packages, that you would want to build a communications module with ethernet and or USB, and equip it with multiple SPI interfaces, unless the extra 1us required to read out the ADCs is crucial. By building the analog boards separately, you can use less expensive (ie 2-4 layer no bga) tech. And you could configure your analog boards for whatever inputs/outputs you desire. I would be interested in participating anyway.

mike