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| Revision | Operations | |
|---|---|---|
| 15/06/2010 - 10:20 by lilltroll | current revision | |
| 06/06/2010 - 21:32 by lilltroll Added VU meters | ||
| 20/05/2010 - 15:57 by lilltroll | ||
| 19/05/2010 - 12:42 by lilltroll | ||
| 19/05/2010 - 12:40 by lilltroll | ||
This project aims to post updated source code that runs on the XDK-G4-XAI code - proven to work under XDE 10.4 and with the XAI on the right side on the XDK.
Ckeck out the XAI user guide for DIP-Switches settings on the XDK at "https://www.xmos.com/published/xaiqs"
XMOS is planning to release updated code in the future - but until that date - feel free to begin with this one!
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Ver 1.3
Added:
Linebuffer to the LCD
Buttons & Leds
Touchscreen
Graph/data vier with 144 dB of zoom in Y-led based on touch
Channel 1&2 are sent to DSPcore(0) & DSPcore(1) where resampled 1:24, then loopbacked.
Channel 3,4,5,6 are loopbacked directly.
2 empty screens for user code (Black and Blue) buttons
Not yet tested or optimized above 44.1 kHz
VU meters
Added VU meters + 6->6 channels loopback (reversed stereo chan)
Total latency | Codec in slave mode
With a MCLK/BLCK = 2 we can achieve fs=200 kHz with a MCLK=25.6 MHz
There is no danger to starve the XMOS out of time due to a very high MCLK.
But as the code is implemented it's not possible to run the thread in 50 MHz and fs @ 200 kHz; the process will be starved out of time. And this is only for stereo in - stereo out.
Is it really possible to run 6 channels in and 8 channels out at 192 kHz. At the moment I'm not sure at all. But using more active channels shouldn't be a headache for the I2S routine since all date is streamed in only one XMOS channel.
The latency is around 110us at 200 kHz.
Total latency | Codec in master mode
The Clock synthesizer can generate clocks up to 75 MHz.
The CODEC doesn't want frequencies above 51.2 MHz, but that's too high speed anyway for an unbuffered XMOS serial inport ( in port wck).
Up to 45 MHz seems to work during test.
Thus, 176.4 kHz fs is on the limit in master mode (MCLK=45.1284 MHz)
with a 256xFs QSM => Latency = 111 us.
Lowest possible MCLK=6 MHz => fs=11718,75 Hz @ 512xFs- SSM => Latency = 2.4 ms