Hi everybody,
I'm currently defining the operational modes this XLink Memory Service Board will be offering to the XCore programmer (streaming data file | random access | structured data repository | ???...).
So, if anybody has an interest into it, you're welcome to let me know what your ideas, dreams, wishes, ... are ;-)
https://www.xcore.com/projects/xlink-l- ... vice-board
Thanks in advance
Al
XLink Non-volatile Memory Service Board : comments welcome
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Allein
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Ross
- XCore Expert
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sounds interesting!
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kster59
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Any target price of the FPGA?
If it's more than $8 it's easier just to use an ARM.
We also needed something like this but then just bought an ARM to handle the SDRAM coprocessor. ARM chip is around $5-8 and 32mb SDRAM is $3 for a total cost of around $11-15.
We also offloaded the Ethernet, USB and SD card to the ARM so this actually saved quite a bit.
If it's more than $8 it's easier just to use an ARM.
We also needed something like this but then just bought an ARM to handle the SDRAM coprocessor. ARM chip is around $5-8 and 32mb SDRAM is $3 for a total cost of around $11-15.
We also offloaded the Ethernet, USB and SD card to the ARM so this actually saved quite a bit.
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Allein
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Speaking about this board details:
- Target price: the BOM is not yet fully completed but offering a non-volatile MRAM bank functionality can't compete with a low-price SDRAM; re: FPGA, the Lattice entry-level FPGAs are fully competitive with the mentioned $8 scale.
- Target functionality: MRAM chips are non-volatile, fast (in a similar architecture but not XMOS based, we do achieve less than 20ns random access time) and offer unlimited endurance, so not to be compared with an SDRAM bank...
- Target performance: the XLink channel service will be 5w, streamed, so 250Mbps or 31MBps. And this bandwidth can easily be sustained by both the FPGA and the MRAM chips. And we'll have 2 to 4 channels able to operate concurrently, so this B/W will be available to 2 to 4 XCores.
How does your ARM implementation compare with this ? I'd be very interested in learning a bit more of the performance figures you achieved with your XLink implementation.
This implementation isn't targeting extreme-low-cost, simple mass solutions, but will find its place from low- / middle-end, powerful solutions on, up to complex high-bandwidth and parallel applications.
But for sure, this service will not be expansive with regards to the offered complementary mix of high-performance, concurrent access paths and unlimited non-volatile memory.
- Target price: the BOM is not yet fully completed but offering a non-volatile MRAM bank functionality can't compete with a low-price SDRAM; re: FPGA, the Lattice entry-level FPGAs are fully competitive with the mentioned $8 scale.
- Target functionality: MRAM chips are non-volatile, fast (in a similar architecture but not XMOS based, we do achieve less than 20ns random access time) and offer unlimited endurance, so not to be compared with an SDRAM bank...
- Target performance: the XLink channel service will be 5w, streamed, so 250Mbps or 31MBps. And this bandwidth can easily be sustained by both the FPGA and the MRAM chips. And we'll have 2 to 4 channels able to operate concurrently, so this B/W will be available to 2 to 4 XCores.
How does your ARM implementation compare with this ? I'd be very interested in learning a bit more of the performance figures you achieved with your XLink implementation.
This implementation isn't targeting extreme-low-cost, simple mass solutions, but will find its place from low- / middle-end, powerful solutions on, up to complex high-bandwidth and parallel applications.
But for sure, this service will not be expansive with regards to the offered complementary mix of high-performance, concurrent access paths and unlimited non-volatile memory.
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Folknology
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kster59 do you have any details about your ARM implementation, is it open source, which chip did you use as I could really use something like that.
regards
Al
regards
Al