Extended XS Port Map

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kevpatt
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Posts: 21
Joined: Thu Feb 09, 2017 4:53 pm

Extended XS Port Map

Postby kevpatt » Wed Mar 22, 2017 7:14 pm

I've put together a little chart showing the full "potential" XS portmap. I'm trying to combine various bits of relevant information that is found throughout the datasheets but is not always included in the given portmap. For example, I like to know which ports will be unavailable due to USB or RGMII (ethernet) use. The portmap shows the physical pins used for RGMII, but there are additional ports that are used internally, discussed elsewhere in the datasheet. The idea here is to get all the information in one place.

Thoughts or ideas for improvement?

Here's a pdf of what I have so far.

Caveats:

* I have not thoroughly double-checked everything in this chart. There may be errors. Use at your own risk.
* The most important thing to keep in mind is the fact that most xCore devices do not bond out all ports fully. So, you'll need to "delete" (i.e. ignore) rows from the table that are not present on your device package. Also, which pins are bonded often varies from tile to tile on the same device.
* Not all devices implement all functionality. For example, an XL or XLF device does not have USB or RGMII.
* The "power" column shows ports that are associated with RGMII physical I/O; these are powered by the IOT pin and are often 2.5V for GbE PHYs. If you have a 3.3V PHY or are not using Ethernet, you can power IOT at 3.3V. Devices with two RGMII interfaces (four-tile devices), have separate IOT and IOT_2 supply pins for each RGMII.
* The "drv" column shows 8ma output drivers (as opposed to standard 4ma) that are associated with RGMII outputs. If your device has RGMII functionality, these pins are 8ma drive whether or not you enable Ethernet!
* The gray "xLink" identifiers are for two-tile XS2 devices. (In four-tile XS2 devices, these links are appear on tiles X2 and X3, not X0 and X1.)
* The gray bracketed text under USB and RGMII indicates ports that are used internally when that functionality is enabled.
* Under RGMII, SMIO and SMC are in parentheses because they can be implemented on other 1-bit ports if desired, but are conventionally located here.

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matthew1
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Joined: Mon Oct 19, 2015 2:12 pm

Postby matthew1 » Fri Mar 24, 2017 2:12 pm

Hi,

have you taken a look at the xCORE-200 port map:

http://www.xmos.com/doc/XM-007017-PC

I hope that might help with some of your requirements?

Regards,

Matthew.
XMOS
kevpatt
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Posts: 21
Joined: Thu Feb 09, 2017 4:53 pm

Postby kevpatt » Fri Mar 24, 2017 6:47 pm

matthew1 wrote:Have you taken a look at the xCORE-200 port map:
http://www.xmos.com/doc/XM-007017-PC


Wow, thanks! I haven't seen that document before. Definitely has a lot of the information I'm looking for in one place. :)

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