8-ch audio card USB Bus Problems

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hamtam
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8-ch audio card USB Bus Problems

Postby hamtam » Thu Jan 18, 2018 1:27 pm

I build a 8ch Sound car with a 4 Layer PCB.
    Signal
    PWR
    GND
    Signal

I probably have problems on the USB side. My Card is bus powerd and draw between 450 and 500 mA. I calculated the USB Bus with about 100 Ohm but it has only 22mm.

As you can see from my calculation the width of the tracks are 0.25mm with a gap of 0.15mm.
Image

Code: Select all

[33656.321046] usb 3-1.3.2: USB disconnect, device number 18
[33660.299860] usb 1-5: USB disconnect, device number 20
[33665.865270] usb 1-6: new high-speed USB device number 25 using xhci_hcd
[33666.006096] usb 1-6: New USB device found, idVendor=2f3f, idProduct=2001
[33666.006100] usb 1-6: New USB device strings: Mfr=1, Product=3, SerialNumber=2
[33666.006102] usb 1-6: Product: CONET 8-ch-sc
[33666.006105] usb 1-6: Manufacturer: CONET Solutions GmbH
[33666.006106] usb 1-6: SerialNumber: 932184B3
[33671.062142] usb 1-6: parse_audio_format_rates_v2(): unable to find clock source (clock -71)
...
[33671.269216] usb 1-6: 1:1: usb_set_interface failed (-71)
[33676.377782] usb 1-6: cannot get ctl value: req = 0x81, wValue = 0x101, wIndex = 0xb00, type = 1
...
[33671.087823] usb 1-6: 10:0: cannot get min/max values for control 2 (id 10)                                                               
[33671.087902] usb 1-6: cannot get ctl value: req = 0x83, wValue = 0x201, wIndex = 0xa00, type = 4


Alsamixer Ends with the message
cannot load mixer controls: Protocol error
.

I have an continuous GND plane under the bus tracks. The current board has no keep out between the USB Bus tracks.
Image

Image

The 24MHz Master Clock looks good on the oscilloscope.

The Debugger said but I do not know if it is related:
tile[1] core[2] (Suspended: Signal 'ET_LOAD_STORE' received. Description: Memory access exception.)
4 handle_audio_request() decouple.xc:493 0x00041b64
3 __kent() 0x00040766
2 __main__main_tile_1_task_decouple_4() main.xc:185 0x00040d0d
1 <symbol is not available> 0x00000000
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mon2
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Postby mon2 » Thu Jan 18, 2018 4:37 pm

Can you post the schematics for the design? The issues could be s/w or could be h/w related.

Aside from the audio IP, can you apply and run XMOS USB CDC or some other canned USB IP on your custom board? Does that work ok?
hamtam
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Postby hamtam » Fri Jan 19, 2018 8:12 am

I orientated towards the xcore200 Dev Board.
https://www.hamtam.de/conet/8-ch-soundcard.pdf

I am able to get sound in and out but it works not reliable.

I must confess that I am not sure about XMOS USB CDC and other USB IP. We adapted the Software of XMOS xCORE-200 USB Audio.
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Postby mon2 » Fri Jan 19, 2018 5:26 pm

Do not see the protection on Vbus rail which is required to prevent early death to the XMOS CPU.

A poor man's version is the following circuit - more elegant solution is to insert a valid USB load switch with soft-start, reverse voltage protection, etc. (ie. Diodes Inc. APA2822AKA is one of many choices - be sure to cross check the pinout against distribution inventory - some footprints are more popular than others):

Image

viewtopic.php?f=7&t=5589&hilit=vbus+protection
hamtam
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Postby hamtam » Mon Jan 22, 2018 7:53 am

Thank you for the advice. But I am wondering if it is not enough that I have VBUS connected with the Step up Buck down converter. Thus, the xcmos should be protected.
I think the problem is more with the USB Signalling. As the xcore do not respond on any USB requests (see log snipped).
Ho do you design te USB Bus do you use TVS Diodes or do you connect without any protection?
I suppose that the protection Diodes produce reflections on the USB Bus.
How can I debug the USB Bus?
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Postby mon2 » Mon Jan 22, 2018 9:03 am

Reflash your custom pcb to become a USB CDC function using the XMOS appnote. What are the results?

Then test with USB HID ip. What are the results?

https://www.xmos.com/support/appnotes?subcategory=USB%20examples

From the logs, the initial USB header info appears to be solid so these tests will validate the USB operations at the various bus speeds.
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mon2
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Postby mon2 » Mon Jan 22, 2018 9:18 am

hamtam
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Postby hamtam » Thu Feb 15, 2018 10:29 am

The solution was:
    - to remove the ESD Protection
    - calculate the bus for an FR4 Material with a high of 0,1mm between GND and Signal
    - backtrack the copper from the bus lines.
Now I do not have the USB Bus problems any more.
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Postby mon2 » Thu Feb 15, 2018 12:14 pm

Thanks for your update and post. ESD protection is very important to have for your device. Consider to use the Socay ULC0524P which is very low capacitance and works very well. Socay is in Shenzhen and supplies many parts to others under private label. We use them all the time for our products. This part is available under other brands with the same footprint through Digikey, Mouser, etc. for your testing. Socay price is under $0.10 usd in single T&R qty for this component.

Glad to hear you have it working!!
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Postby mon2 » Thu Feb 15, 2018 1:22 pm

Hello again hamtam. The TI ESD part you have applied should be fine for use with USB 2.0 HS modes. While we are not Dr. Howard Johnson on this subject, have the following highlighted traces that should be fixed on your next PCB layout.

reference:

http://www.ti.com/lit/an/spraar7g/spraar7g.pdf

http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf

* use symmetric traces for the HS USB lines
* no stubs on these USB data lines
* be sure to highlight your USB traces to your PCB supplied (before sending out for the PCB run) and request that they exercise impedance control for this critical portion of the design + offer proof with a TDR test report that they followed your request. Most PCB shops will perform this service for low ($10 USD) or for "free". We use Tiefa PCB in Shenzhen (Chantal is our contact) and they are very fair on our prototypes pcb runs. Have used them for at least 2 years to date. Another good shop is Kingford PCB. More expensive than Tiefa but have met them and they have more capabilities for more complex PCBs.

Image

The USB 2.0 HS D+ / D- traces cannot have stubs and traces as shown in the above graphic. For example, the left trace run for D+ should be removed and is redundant. The 90 degree jog to the left is creating a stub. Please review the PCB gerbers from XMOS for this topic. They have used this same TI ESD component on many of their designs to date.

Comment: Personally not a PCB designer but have many high volume widgets in the field with no issues. ESD is real and is required. We have had zero field failures after properly applying such devices. For giggles, take a sharp knife and cut the 90 degree jog on D+ near the USB connector (near the X symbol). Do the same at the end of the same trace near the XMOS device. That is, ONLY have a single clean start and end trace to the XMOS device for D+. Then solder back the TI part and check the results. Please post here when you can. Also remove the dip of the trace for D- line in your next PCB layout. Be sure that these same traces are not crossing any PCB planes in the other layers. Do confirm with your PCB shop that the layout is suitable and impedance control can be met. This is a factor linked to the laminate they will use for your production. Best to compare against XMOS ref designs for guidance on this TI part layout.

https://www.xmos.com/support/boards?pro ... nent=19780

https://www.xmos.com/support/boards?pro ... nent=19739

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