Is the XMOS instruction set liable to change?

[dave]

As far as the pipeline goes. There is never more than one instruction from any specific thread in the pipeline. One stage in the pipeline is used for memory access. For branch instructions, this stage is used to fetch the instruction(s) at the branch target if the branch is taken. There is no need for a branch target cache. The timing is the same whether or not the branch is taken.

[Heater]

Thank you David.

The lesson is clear, as a veteran cycle counter I have to foster the habit of using the available timing facilities, clocked ports, serializers etc instead. Oh, and be careful with divides.

Good to hear that branches have the same execution time whichever way they go, I'm sure I will find myself counting cycles sometimes.

Speaking of which I understand that soon there will be a tool to perform timing analysis. I'm intrigued by this idea. I have only ever worked with one compiler that could report the exact execution time of your programs. That was Lucol from Lucas Aerospace.

[leon_heller]

There already is a tool for that, it's xta.exe. Download the tutorial (xtatut.pdf).

Leon

[yzoer]

Thank you David.

The lesson is clear, as a veteran cycle counter I have to foster the habit of using the available timing facilities, clocked ports, serializers etc instead. Oh, and be careful with divides.

Good to hear that branches have the same execution time whichever way they go, I'm sure I will find myself counting cycles sometimes.

Speaking of which I understand that soon there will be a tool to perform timing analysis. I'm intrigued by this idea. I have only ever worked with one compiler that could report the exact execution time of your programs. That was Lucol from Lucas Aerospace.

I went through similar growing pains trying to get the VGA and NTSC timing up and running. Apart from non-timing critical performance optimizations, relying on clocked-ports is really the way to go! Absolutely brilliant!

-Yvo