Synchronize start_clock() with external gate

[psebastiani]

Hi
I have necessity to synchronize the start_clock() to specified external rising edge signal.
I have defined:

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on stdcore [2]: clock SysClk = XS1_CLKBLK_1;
on stdcore [2]: out port SysClkPort = SYS_CLK;

with this configuration:

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configure_clock_rate(SysClk, 50, SYS_CLKPERIOD); // 50/50 -> 1 MHz
configure_port_clock_output(SysClkPort , SysClk); //OutPort clock output

I must receive an external gate signal from this port:

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on stdcore [2]: in port TriggerGateIn = TRIG_GATE_IN;

The rising edge of this signal (TriggerGateIn) must be the event that start the previus clock. This event must synchronize the the start of SysClk: start_clock(SysClk);

There is any way to do this?
Regards

[sethu_jangala]

Hello,

It is possible to use an external clock. You can input the clock signal using a port and perform operations based on input clock. The following link gives you more information about clocked IO operations.
https://www.xmos.com/en/support/documen ... 806&page=3

Sethu.

[psebastiani]

Hi
thanks for reply

I can configure external pin as clock:

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configure_clock_src(TrigGateClk, TriggerGateIn);

but I don'have any port to link at this event.
What is the event that i can monitor to verify the commutation of this gate pin?


At this moment I simply polling this pin, and when it's equal to 1, the clock is activated with start_clock() function.
In this mode i have few nanosecond of delay that i should to reduce.
Also I have another little problem:
The function start_clock() starts with low-level first, them hi-level.
I want this clock normally at zero, and start with the hi-level first.
I try with set_port_inv() but in change the "normally" state to 1.

Piero.

[sethu_jangala]

Hi,

You can use "select" statement to monitor the pin. Also, you can use clocked buffered ports for the other issue. You can set the port as clocked buffered output port and you can put data on to the ports when there is an external event on input port.

Document on buffered ports is available in the following link:
https://www.xmos.com/en/support/documen ... 806&page=4

Hope this helps.

Sethu.

[Ross]

Does this gate line remain high for the duration of the clocking?

Does the clocking continue indefinitely after this gate signal or is it a burst of communication?

Could you provide a timing diagram? I'm not sure I understand this issue properly.

At this moment I simply polling this pin, and when it's equal to 1

Polling is not ideal, assuming you mean something like the following:

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unsigned x = 0;
while(!x)
  p_gate_port :> x;

You should use a statement similar to the following:

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p_gate_port when pinseq(1) :> void;

This will reduce power consumption and should be more deterministic.

[psebastiani]

Hi Ross
You suggest me a good solution

My goal is explained in the first figure.
I have a single pulse, and i must sincronize the Out_clock to the rising edge of this pulse.
Syncronize or with minimal and deterministic delay.
With your suggestion i have reduced this delay.

I have also another problem; see second image.
I generate the Out_clock with the function start_clock(), and this function go out first the low level and then the high level. In this mode i have always half period delay!
There are any way to avoid this? I wanto this start with the high level.
I have tried with set_port_inv() function, but this invert all output signal; this remain high when the clock is unused, and this is not good for me.