At xTimecoposer v13.2.2 can't upload to flash memory.

Technical questions regarding the XTC tools and programming with XMOS.
choya8152
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Posts: 3
Joined: Fri Feb 13, 2015 5:25 pm

At xTimecoposer v13.2.2 can't upload to flash memory.

Post by choya8152 »

I trying to upgrade latest XTCP(3.2.1rc1), Ethernet(2.3.2rc0) and AVB module on XS1-G04.
but, the firmware failed to upload on flash device.

I have some question.

1. I tried the UDP test. but it occur error in debug mode.(mii_free))
- When we send a UDP packet to XS1-G04 with interval time in 500ms, work well.
but, When we send a UDP packet to XS1-G04 with interval time in 100ms, Error occur from mii_free.

2. when trying to write the flash, as following errors occurred.
- xrun: First stage multi-node boot failed, please check XN file and Xmos link connectivity

I would like to know that how to upload at to flash via XS1-G04.

The attachment file is flash setting and device configuration.

thank.

Code: Select all

<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
  <Type>Device</Type>
  <Name>XS1-G04B-FB144-C4 Device</Name>

  <Declarations>
    <Declaration>core tile[4]</Declaration>
  </Declarations>

  <Packages>
    <Package id="0" Type="XS1-G4B-FB144">
      <Nodes>
        <Node Id="0" InPackageId="0" Type="XS1-G4B" Oscillator="20Mhz" SystemFrequency="400MHz">
          <Core Number="0" Reference="tile[0]">
          	<Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO" />
			<Port Location="XS1_PORT_1B" Name="PORT_SPI_SS" />
			<Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK" />
			<Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI" />
			</Core>
          <Core Number="1" Reference="tile[1]"/>
          <Core Number="2" Reference="tile[2]">
          	<Port Location="XS1_PORT_8A" Name="PORT_SW_IN" />
          	
          	<Port Location="XS1_PORT_1A" Name="PORT_ETH_RXCLK"/>
          	<Port Location="XS1_PORT_1B" Name="PORT_ETH_RXER"/>
          	<Port Location="XS1_PORT_1C" Name="PORT_ETH_TXCLK"/>
            <Port Location="XS1_PORT_1D" Name="PORT_ETH_RXDV"/>
            <Port Location="XS1_PORT_1E" Name="PORT_ETH_TXEN"/>
            <Port Location="XS1_PORT_1G" Name="PORT_ETH_MDIO"/>
            <Port Location="XS1_PORT_1H" Name="PORT_ETH_RST_N"/>
            <Port Location="XS1_PORT_1I" Name="PORT_ETH_MDC"/>
            <Port Location="XS1_PORT_4C" Name="PORT_ETH_RXD"/>
            <Port Location="XS1_PORT_4D" Name="PORT_ETH_TXD"/>
            </Core>
          <Core Number="3" Reference="tile[3]"/>
          <Boot>
			<Source Location="SPI:bootFlash" />
		  </Boot>
        </Node>
        
      </Nodes>
    </Package>
  </Packages>
  

   <ExternalDevices>
		<Device NodeId="0" Tile="0" Class="SPIFlash" Name="bootFlash" Type="AT25DF081A">
			<Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO" />
			<Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS" />
			<Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK" />
			<Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI" />
		</Device>
	</ExternalDevices>

  <JTAGChain>
     <JTAGDevice NodeId="0"/>
  </JTAGChain>

</Network>

Code: Select all


0,
256,                    /* page size */
4096,                   /* num pages */
3,                      /* address size */
8,                      /* log2 clock divider */
0x9F,                   /* SPI_RDID */
0,                      /* id dummy bytes */
3,                      /* id size in bytes */
0x1f4501,               /* device id */
0x20,                   /* SPI_BE4 */
4096,                   /* Sector erase is always 4KB */
0x06,                   /* SPI_WREN */
0x04,                   /* SPI_WRDI */
PROT_TYPE_SECS,         /* no protection */
{{0,0},{0x36,0x39}},    /* SPI_SP, SPI_SU */
0x02,                   /* SPI_PP */
0x0B,                   /* SPI_READ_FAST */
1,                      /* 1 read dummy byte */
SECTOR_LAYOUT_REGULAR,  /* mad sectors */
{4096,{11,{8,8,8,8,8,8,8,7,5,5,6}}},  /* regular sector sizes */
0x05,                   /* SPI_RDSR */
0x01,                   /* SPI_WRSR */
0x01,                   /* SPI_WIP_BIT_MASK */

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