optical Rx and Gigabit: tile full

[leutholl]

Hi

Trying to read audio samples from the optical Rx which is hardwired to tile 1 on my xCore200-MultiChannel Board. There is also the Gigabit Library which takes the full tile 1 so I cannot run any task to handle the data coming from the optical Rx. Tile 0 would be available but can't speak to the optical Rx port on tile 1...

Is there a way to:
- redirect the optical Rx port to tile 0 without running a task either by software or rewiring something (is there a handy header pin available on this board to insert a jumper cable?)
- how to change the gigabit library to reduce the number of tasks/core in 100MBit/s mode (I don't need Gigabit). This library is way too big to find the spot where the full 8 tasks are spun up - at least for me. Somebody else asked for this, but didn't got any "ready-made" answer.

Anybody did some ADAT Rx in combination with the Ethernet going?

Thanks for your help!

[infiniteimprobability]

Is there a way to:
- redirect the optical Rx port to tile 0 without running a task either by software or rewiring something (is there a handy header pin available on this board to insert a jumper cable?)

You can't do it interally without running a task. The two tiles are separate and the only internal connections are the core clock, JTAG and links. Links mean you would need to have a software task on both sides to talk.
However, on the board is a via (which you can solder a header into) called O_RX just by the crystal. This is the line that goes to the 1b port on tile 1. You could connect this to O_TX which goes to the optical transmitter and port 1E on tile 0. Since the optical transmitter is an input, this will work fine and you'll just get a copy of the signal for kicks..

- how to change the gigabit library to reduce the number of tasks/core in 100MBit/s mode (I don't need Gigabit). This library is way too big to find the spot where the full 8 tasks are spun up - at least for me. Somebody else asked for this, but didn't got any "ready-made" answer.

There are smaller variants of Ethernet for 100Mbit (As small as 3 cores) which use MII but... the PHY used on the board expects an RGMII interface that requires all of the extra cores to get the required performance, even at 100Mb or 10Mb link speed.. So you would need to add an MII PHY to get the core saving from these lower performance versions of lib_ethernet.

Anybody did some ADAT Rx in combination with the Ethernet going?

Not personally! I had AVB running with SPDIF Tx and that was OK. Connecting Ethernet to digital Rx will require some variable size buffering or ASRC though I would have thought.

[peter]

If you want to reduce the RGMII core usage I've described how that can be done in this post:

http://www.xcore.com/viewtopic.php?f=26 ... res#p24242

[leutholl]

Thank to all of you!
I got:
- a reduced library of the RGMII - thanks to peters input! As I'm sending only and don't need any MAC functionality I guess it could even be stripped down further - but the library is too huge for me to fully understand. Maybe you have another pointer on where to remove code?!

- I will order the slice kit together with 2 MII PHY and try the magic here

- I have ADAT running (however got a syncing problem - see my other thread) with I2S. Next up will be ADAT to my Ethernet which (after saving some cores in tile 1) should be straight forward and possible to do. Having that and without any need for I2S, I must further understand how to clock/slave my entire board by the incoming ADAT clock (PLL?). Interestingly my Ethernet packets don't have to follow a tight timing - I guess the receiving far end will somehow forgive packet jitter by buffering some packets. Still I want to avoid ASRC.

Thanks again!