Setting up an Clock block from MCLK input

Technical questions regarding the XTC tools and programming with XMOS.
Post Reply
Dohny
Member++
Posts: 26
Joined: Tue Dec 03, 2013 6:57 pm

Setting up an Clock block from MCLK input

Post by Dohny »

Hi guys,

I need to get 768/705.6 kHz (90.../98... MCK divided by 128) on 1 bit port on tile 0 of my XUF216 running USB audio SW for synchronizing external circuitry. I wanted to use an clock block which is initialized from audioports.xc on tile 0 like this:

Code: Select all

  
  /* Clock bitclock clock block from master clock pin (divided) */
    configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
    configure_port_clock_output(p_bclk, clk_audio_bclk);

    configure_clock_src_divide(clk_pwr, p_mclk_in, 64);
    configure_port_clock_output(p_clkpwr, clk_pwr);
    .
    .
    .
    /* Start clock blocks ticking */
    start_clock(clk_audio_bclk);

    start_clock(clk_pwr);


    #else /* CODEC_MASTER */

    /* Stop bit and master clock blocks */
    ...
    
I'm using mclk input port as a clock source, output port is defined like buffered 32 bit (I also tried unbuffered) and clock block I'm using is CLKBLK_SPDIF_RX as I don't have SPDIF RX running.

I get very nice MCK/128 clock output on my clk_pwr port. Problem is that my USB audio is no longer working... LRCK and SCK are running at the beginning, but the moment I start streaming audio they disappear and whole software crashes. It's still enumerated but cannot play any audio.

Any idea whats wrong? Or maybe a better solution?

Thanks.


User avatar
infiniteimprobability
XCore Legend
Posts: 1126
Joined: Thu May 27, 2010 10:08 am
Contact:

Post by infiniteimprobability »

It's not immediately clear to me what has happened here - You have setup the clock and port OK. Actually the type of port buffering doesn't matter when it's a clock output, as you have found. It's also valid to have multiple clock blocks being clocked from the same port.

Does the clk_pwr signal disappear too at stream start?

When you do stream start, the audioports.xc code gets executed (ConfigAudioPortsWrapper and ConfigAudioPorts) to setup the ports before streaming... that's the place to start looking.
Dohny
Member++
Posts: 26
Joined: Tue Dec 03, 2013 6:57 pm

Post by Dohny »

No, CLK_PWR is still running happily...its just audio clocks that are gone. I'm looking but dont see anything obvious sadly.
Is this clock block a hardware block with hardware divider? Or is it some kind of software bitbanging?
User avatar
infiniteimprobability
XCore Legend
Posts: 1126
Joined: Thu May 27, 2010 10:08 am
Contact:

Post by infiniteimprobability »

Is this clock block a hardware block with hardware divider? Or is it some kind of software bitbanging?
Yes - it's a hardware divider.

In recent builds of USB audio, the hardware divided bit clock is used. So SCLK is hardware divided and LRCLK is *bit banged along with the data.

*Well kind of more sophisticated than bit banged. The values are accessed as 32b and an internal buffered shift register clocks in/out.

So the interesting thing in your case, is that the SCLK output stops at stream start which means it's to do with the clockblock and port input interaction. If SCLK is not present then the I2S loop outputting LRCLK and data will halt (code will be block on I/O instruction because transfer register full).

Thinking about this, it feels like some sort of dependancy on a 1b port already being used to clock a clock block... but this doesn't seem right as multiple clock blocks from a single port *should* be OK. What happens if you put the enable clk_pwr code after the audioports code?
Dohny
Member++
Posts: 26
Joined: Tue Dec 03, 2013 6:57 pm

Post by Dohny »

Same thing, doesn't really matter where I init/start the clock block :( I had to deal with it for this design with external counter...but would be nice to have it working for future designs... Maybe next time I just put another MCK 1b port to tile 1 and run it there.
MaximLiadov
XCore Addict
Posts: 130
Joined: Mon Apr 16, 2018 9:14 am

Post by MaximLiadov »

...
Post Reply