Need help with XU208 bulk device and IO sampling

Technical questions regarding the XTC tools and programming with XMOS.
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xchips
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Need help with XU208 bulk device and IO sampling

Post by xchips »

I’ m using XU208 to implement a bulk transfer and IO sampling device, the simple block diagram is as following:
XU208_BLK_DIAGRAM.png
XU208_BLK_DIAGRAM.png (12.17 KiB) Viewed 5743 times
XU208_BLK_DIAGRAM.png
XU208_BLK_DIAGRAM.png (12.17 KiB) Viewed 5743 times
But for now, the sampling clock can only up to 6.25MHz. Any clock > 6.25MHz will return wrong data from XU208.

Test method
I use some FPGA codes to output sequence data to instead a real ADC chip, so that I can test the sampling clock easily.
App will save the bulk data as a binary file.
Then I use some C codes to verify the sequence data on PC side. If non-sequence data has been found, C code will tell.

How to implement this bulk transfer, IO sampling device?
There are 3 threads on XU208 device (not include USB device manager thread and Endpoint0 thread).
Thread A: USB bulk transfer thread (For bulk endpoint), transfer data to USB device manager thread.
Thread B: Data handling thread, transfer data to A by transferring movable pointer.
Thread C: IO sampling thread, IO sampling and transfer data to B (use unsafe pointer to share memory with B).

Summary for this issue
1. If I generate sequence data in Thread C but not sample IO from FPGA. I can get correct data back no matter what frequency the sampling clock is.
2. Or the max sampling clock only can be 6.25MHz.
3. I had tried using the channel type to exchange between Thread B and C, but no improvement, and after I used unsafe pointer to exchange data between
Thread B and C, I think it isn’t the bottleneck anymore, but I still can’t make the sampling clock > 6.25MHz.

I felt confused about this and I don’t know what to do next, also I’m not sure what I wrote is simple and clear enough but I really need some help.
Any idea will be appreciated.

Attached please find my project if you are interested in it.
XU208_BULK_IO_SAMPLING.xc
(22.25 KiB) Downloaded 230 times
XU208_BULK_IO_SAMPLING.xc
(22.25 KiB) Downloaded 230 times


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akp
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Post by akp »

This is probably of no help but if it works at low speed but not high speed the most likely causes would be:
1. Your software is too slow (can't handle the processing between new samples becoming available)
2. Your hardware has a signal integrity issue or setup/hold time violation

Have you reduced the processing in the Thread C (IO sampling thread) since the sampling is obviously the problem if generating data rather than sampling fixes the issue.
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mon2
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Post by mon2 »

Just brainstorming like akp so...

1) you appear to be creating the differential clocks via s/w for your external DDS device. Consider to allow the XMOS to generate the desired clock value using a single port pin but interface a low cost external RS422 transceiver that is not slew rate controlled. Check MAX3079 or Intersil for such parts which are rated for 16Mbps to 20Mbps or even faster. The focus is to be sure that the differential clock is aligned properly for the DDS.

You could even consider to use the Adafruit PCB with the Silabs Si5351A PLL w/25 Mhz ref crystal -> mate to your XMOS CPU over I2C -> now you can dial up any clock value of your choice to sample at custom rates with the DDS -> feed this 3v3 clock PLL output to your XMOS CPU and still add an external RS422 transceiver to generate the differential clock for the DDS.

Code to program the Silabs' PLL with Startkit is posted here:

http://www.xcore.com/viewtopic.php?f=7&t=4599

This will relieve the burden of the XMOS CPU generating only selective clock taps for your DDS sampling.

2) DDS is configured correctly for your setup ? Recommend to compare register settings against other similar implementations as a confirmation.

3) How far is the DDS from the XMOS port pins ? At 3v3 and relatively high data rates, the devices should be close and on a multilayer PCB. If you have cabling connecting the XMOS CPU and the DDS then this could be a factor.
xchips
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Post by xchips »

@akp
Thank you very much for your ideas.
#1, My 12-bit ADC bus is a combination of 3x 4-bit ports, so I don't know if there is another method that faster than a buffered: 32 port:
in buffered port:32 p_qa8_11 = XS1_PORT_4C;
in buffered port:32 p_qa4_7 = XS1_PORT_4E;
in buffered port:32 p_qa0_3 = XS1_PORT_4F;
Can I have your better port definition please (or handling method)?

@akp & mon2
Thank you very much for your HW part ideas.
I guess I have to check the IO data internally in MCU first, to make sure there is no any timing issue.

@mon2
I got a si5351A PLL in my hand, indeed. I'm not sure if the differential clocks can work correctly, but for now, the ADC part (the block diagram above) is instead by FPGA and only use the clk_p, clk_n is floating.
So the DDS is not using for this test.

The du-pont wire between FPGA and XU208 is about 15cm.

Thanks again!
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mon2
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Post by mon2 »

The du-pont wire between FPGA and XU208 is about 15cm.
This could be the show stopper here since the signals are single ended @ 3v3 swing and not differential, the wiring should be as short as possible and 15cm is quite long for these data rates.

Check the signal quality with a scope to see what is being sent by the FPGA side of the wire and compare to the what is being received on the other side of the same wire by the XMOS CPU. If it is not possible to reduce the wiring length then consider the use of shielded cables (data + shield ground) for each such signal.

If you expect to have some distance between the XMOS CPU and the remote DDS controller then you must review how to maintain the signal integrity of all such interface signals. Some ideas are to consider LVDS transceivers or RS422 transceivers for uni-direction signals.

Try to reduce or remove the dupont wire length for this device under test to see if the results improve - for example, consider only the solid male / female header pins (2.54 mm pitch = 0.1") to mate the FPGA and XMOS CPU and test again.

For us, usually at this stage, we proceed to create an initial PCB for proof of concept to remove such wire length issues out of the equation. Recommend at least a 4 Layer PCB and there are many relatively low cost, quickturn PCB shops in Asia that can offer such service.

We have been using Shenzhen Tiefa PCB for the past 2+ years for our (many - almost bi-weekly) initial prototypes and they have been the best in final cost with excellent quality to support our detailed specs using Halogen Free laminates. For volume builds, we use Suntak PCBs, also in Shenzhen. Both are fair on the quality of the silk screen which we rate to be 8/10. If you are after a 10/10 on silk screen quality, then consider JETPCB, Fast Turn PCBs for quick turn protos but the cost will be higher.

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akp
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Post by akp »

If you have a signal integrity issue then series resistors of ~27R +/- might be helpful at all your output pins, and reduce the length of the wiring as mon2 says. You can probably rule SI in or out as the problem before doing a PCB but you'll have to be careful and use your scope wisely.
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