Hi,
Since we can dynamically change the pll settings for XCore-200 devices, is there any way to reduce the power consumption for xu208 when USB is not connected ?
Our custom audio board using xu208 is self-powered with VBus connected to the usb connector, can I insert the code of pll settings somewhere ?
Save power when USB is not connected
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yes you can...but.. Please be aware that the inner loop of usb (sc_xud) expects a minimum of 80MHz to function properly (meet timing) so there is only so far you can go (400/5 = 80). There is no way to cleanly exit xud() with PHY shutdown in the current IP.. Also the PHY I/O timing (inside the chip) is tuned with an expectation of core freq of 500MHz.
It *might* be possible to slow stuff down when USB is not connected and then speed up when it is reconnected without breaking the logic but it has not been tried. USB will certainly not be working properly when the
You can try playing with D.6 /D.7 (system switch & ref clock dividers) and C.6 (Tile clock divider) to see if USB will recover after you clock back up but you must keep in mind that the ref clock must be at most half the core clock speed.
Something like this should scale all of the clocks at their existing ratios:
It *might* be possible to slow stuff down when USB is not connected and then speed up when it is reconnected without breaking the logic but it has not been tried. USB will certainly not be working properly when the
You can try playing with D.6 /D.7 (system switch & ref clock dividers) and C.6 (Tile clock divider) to see if USB will recover after you clock back up but you must keep in mind that the ref clock must be at most half the core clock speed.
Something like this should scale all of the clocks at their existing ratios:
Code: Select all
#include <xs1.h>
#include <platform.h>
#define CLOCK_DIV_1 (1 - 1)
#define CLOCK_DIV_100 (100 - 1)
// Enable the clock divider
unsigned xcore_ctrl0_data;
xcore_ctrl0_data = getps(XS1_PS_XCORE_CTRL0);
xcore_ctrl0_data &= 0xffffffff - XCORE_CTRL0_ENABLE_CLK_DIV;
xcore_ctrl0_data += XCORE_CTRL0_ENABLE_CLK_DIV;
setps(XS1_PS_XCORE_CTRL0, xcore_ctrl0_data);
// Change the divider
write_pswitch_reg(get_local_tile_id(), XS1_PSWITCH_PLL_CLK_DIVIDER_NUM, CLOCK_DIV_100);