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AN10129 (1.0.1) - TDM speed
Posted: Tue Mar 20, 2018 7:58 pm
by aelder
The application note explaining how to use zip/unzip has the following comment in the example code:
Code: Select all
// setup clock
configure_clock_rate(bit_clock, 100, 8); // 12.5 MHz
// Note: This proves that a 12.288 MHz bbit_clock works. That's 4 I2S stereo channels at 192kHz
// 25MHz is too fast : configure_clock_rate(bit_clock, 100, 4); // 25 MHz
Why is this? If the bit clock is running at 24.576 MHz, then a 4bit port has to be serviced every 8 bit clocks, which I compute to be every 325 nanoseconds. The zip operations only take 4 cycles, so that is 40 nanoseconds. Is there some other underlying reason for the above statement in the application note?
Re: AN10129 (1.0.1) - TDM speed
Posted: Thu Mar 22, 2018 8:50 pm
by aelder
I'm investigating 32 channels (4 8 channel TDMs) at 96 kHz. I'd like to understand why 25 MHz does not work! What is it about 25 MHz that is too fast?
Re: AN10129 (1.0.1) - TDM speed
Posted: Fri Mar 23, 2018 6:44 pm
by aelder
I've now run the code as well and can confirm the comments in the source code.
Re: AN10129 (1.0.1) - TDM speed
Posted: Fri Mar 23, 2018 8:48 pm
by aelder
I rewrote the processing loop to be
Code: Select all
p_4bit_out <: outputs[3];
p_4bit_in :> inputs[3];
p_4bit_out <: outputs[2];
p_4bit_in :> inputs[2];
p_4bit_out <: outputs[1];
p_4bit_in :> inputs[1];
p_4bit_out <: outputs[0];
p_4bit_in :> inputs[0];
and again, 12.5 MHz bitclock works and 25 MHz bitclock does not. Is there some sort of timing limitation on 4-bit port R/W operations?
Re: AN10129 (1.0.1) - TDM speed
Posted: Sat Mar 24, 2018 2:02 pm
by aelder
Found this
https://www.xmos.com/published/io-timings-for-xcore200 link that implies timings are marginal for externally clock i/o at 25 MHz.
Re: AN10129 (1.0.1) - TDM speed
Posted: Sat Mar 24, 2018 2:48 pm
by akp
Did you run this on the simulator? I'm not sure the simulator will show accurate port timing.
Re: AN10129 (1.0.1) - TDM speed
Posted: Sat Mar 24, 2018 3:57 pm
by mon2
Not sure if it will help but also review the SPI and the QSPI Master ref designs which are being supported at high clk rates:
https://github.com/xcore/sc_spi/tree/ma ... spi_master
https://github.com/xcore/sc_flash
Re: AN10129 (1.0.1) - TDM speed
Posted: Sun Mar 25, 2018 1:00 am
by akp
If you view it in the VCD trace @ 25MHz, the 2nd port value isn't loaded in time so the most significant nibble stays latched for two bit clocks instead of one, which obviously corrupts the input data. Looks to me like it's possibly due to a setc instruction in the inner loop. I don't know enough about low level XMOS programming to know if hand coded assembly could even do it.
The app note bandwidth is the same as 4 TDM channels of 96kHz audio. Maybe you could use 8 x 4 ch TDM to get your 32 channels? That would take 4 x 4 bit ports if you want bidirectional, I guess. Otherwise you will need to use 1 bit ports. With 1 bit ports you can get 4 x 8 ch 96kHz TDM without difficulty.
Re: AN10129 (1.0.1) - TDM speed
Posted: Thu Mar 29, 2018 3:13 pm
by infiniteimprobability
Here's a related thread:
http://www.xcore.com/viewtopic.php?f=37&t=6169
TDM over 4b ports is pretty tough (at least at any sort of useful speed). TDM is so efficient in terms of data ports, why not just use 1b ports?
I'm not sure the simulator will show accurate port timing.
@
akp - it's pretty good actually. The only part of the simulator which deviates from the chip behaviour is the switch. It is functional but latencies and throughputs are not accurate. The ports, ISA, resources etc. are accurate. Most tricky inner loops (including I2S etc.) have been developed with the simulator in part. The great thing is you can see *everything* including transfer register, fill level, buffer register and even port time registers. Loopback is really handy too..
Re: AN10129 (1.0.1) - TDM speed
Posted: Fri Mar 30, 2018 2:51 pm
by aelder
TDM over 4b ports is pretty tough (at least at any sort of useful speed). TDM is so efficient in terms of data ports, why not just use 1b ports?
I actually have 32 channels @ 96kHz in and out as TDM slave working fine in the simulator. I used 4 x 4-bit port2 and I4S on each data line (bit clock is now 12.5Mhz instead of the more challenging 25 Mhz). I ended up having one task dedicated ot i/o and another task that does the zip/unzip and a small amount of processing. I use a shared memory block declared in .asm to support simple pingpong. I know in theory I could use movable pointers and swap operations, but it seemed simpler just to use a block of memory.
Thank you for the comments all.
PS I don't have enough 1-bit i/o to to this with 1-bit ports.