How to decrease the sample rate properly on AN00162?

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
cjf1699
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How to decrease the sample rate properly on AN00162?

Postby cjf1699 » Thu May 31, 2018 5:24 am

Hi everyone,
I am developing an active noise cancellation headphone system on xCORE-200 Multichannel Audio platform, basing on the example: AN00162(Using the i2s library). And now I manage to reduce the noise of single frequencies(i.e. sine waves )from 100Hz - 1000Hz. However, when I change my noise signal to narrowband gaussian noise or just to a double-frequency signal,for example, a signal composed of 400Hz and 410Hz,my system doesn't work. In other words, it can't reduce the noise.
My project is based on LMS algorithm, which is implemented using xCORE-200 DSP library. I tried to increase the order of my FIR filter, but when the order is larger than 70, the project doesn't work——I mean the loudspeaker just make a sound like a bell ring instead of giving a anti-noise that cancels the primary noise, and there isn't any waves on the xSCOPE. I suspect this is due to the larger amount of calculations that need to be done when the filter order increases, and the xcore is unable to handle so much work. So I think maybe a lower sample rate could help solve this. I changed the sample rate from 48k to 24k,16k, 8k,6k,but none of these choices work, the same things happened: bell ring , no waves . So I want to know how to change the sample rate properly ?
Thanks!
cjf
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infiniteimprobability
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Postby infiniteimprobability » Thu May 31, 2018 5:43 pm

There could be any number of reasons for this, but it could well be a timing issue. You can use timers to check you loop timing:

Code: Select all

timer t;
unsigned t0, t1;

t :> t0;
//MY CODE HERE
t :> t1;
if (t1 - t0 > 1900) debug_printf("Argghh taken too long - more than 19 microseconds\n);


Further i2s_master only likes dividers from MCLK of 2^n. You can use i2s_frame_master for arbitrary dividers and so would behave unpredictably for rates like 16000 and related rates. There is an updated AN00162 here https://github.com/xmos/lib_i2s which is in the process of being published which shows you the (very minor) change of API.

Also i2s_frame_master has a LOT more timing margin than i2s_master.
cjf1699
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Posts: 48
Joined: Fri Mar 16, 2018 2:30 pm

Postby cjf1699 » Fri Jun 01, 2018 10:14 am

infiniteimprobability wrote:There could be any number of reasons for this, but it could well be a timing issue. You can use timers to check you loop timing:

Code: Select all

timer t;
unsigned t0, t1;

t :> t0;
//MY CODE HERE
t :> t1;
if (t1 - t0 > 1900) debug_printf("Argghh taken too long - more than 19 microseconds\n);


Further i2s_master only likes dividers from MCLK of 2^n. You can use i2s_frame_master for arbitrary dividers and so would behave unpredictably for rates like 16000 and related rates. There is an updated AN00162 here https://github.com/xmos/lib_i2s which is in the process of being published which shows you the (very minor) change of API.

Also i2s_frame_master has a LOT more timing margin than i2s_master.


Thank you! However, I tried the i2s_frame_callback scheme but it seems that all other frequencies can't be used except for 48kHz,I think I must miss something but I don't know where..

Code: Select all

#define SAMPLE_FREQUENCY 16000
#define MASTER_CLOCK_FREQUENCY 24576000

I changed the SAMPLE_FREQUENCY here, is there anything else that need to be modified?
Thanks again!
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infiniteimprobability
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Postby infiniteimprobability » Fri Jun 01, 2018 11:01 am

I changed the SAMPLE_FREQUENCY here, is there anything else that need to be modified?


No, this is all you need - this directly changes i2s_config.mclk_bclk_ratio which is the key divider.

The MCLK is the clock input and BCLK and LRCLK are generated by the I2S master.

What is happening when it fails? What frequencies do you get on BCLK and LRCLK?
cjf1699
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Joined: Fri Mar 16, 2018 2:30 pm

Postby cjf1699 » Fri Jun 01, 2018 12:49 pm

infiniteimprobability wrote:
I changed the SAMPLE_FREQUENCY here, is there anything else that need to be modified?


No, this is all you need - this directly changes i2s_config.mclk_bclk_ratio which is the key divider.

The MCLK is the clock input and BCLK and LRCLK are generated by the I2S master.

What is happening when it fails? What frequencies do you get on BCLK and LRCLK?

I play a sine wave through two speaker boxes outside(generate stereo) and let the program begins. At the beginning comes a buzz, and then it disappears. Waves can be seen on the xscope but it doesn't reduce noise anymore. In other words, you can't feel any changes if you stop the program at the moment——there isn't any sound being played by the headphone.
My BCLK and LRCLK are all right . The BCLK is 1024MHz and the LRCLK is 16kHz.

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