mon2 wrote:Hi. Could be one of many issues. Please post this relevant cpu, power sequence, power supply and xtag3 schematic of this design in pdf format if possible. Was a reliable contract manufacturer used to assemble this board? Does another pcb behave the same?
Power Sequence: See the attached scope plot. To summarize: VDDIO/OTP (3.3V), CORE/PLL (through a filter) comes up ~440us later, monotonically and within 1ms. Supply values are within spec.
I will attach schematics of the relevant circuits here:
Not sure what you mean re: XTAG3 schematic. The board has an edge connector on it, where the board itself plugs directly into a socket. I then run jumper wires that I soldered to the XMOS XTAG3 board to the PCB that also has the socket. The layout of the test signals themselves probably needs to be revised when we do the next board run, but once I slow the interface down (--jtag-speed 10), when I probe the signals, they look good to me.
Sierra Circuits did the boards. We've used them frequently in the past with good results every time. These boards look very good as well. I looked at the XMOS under the microscope, and there's no visible 'potato-chipping', and the balls that I can see on the perimeter all look to have good adherence and compression. I haven't asked if they were X-ray'ed yet, but I think that is part of their outgoing inspection process.
I've only tested two PCBs to this point. The outward behavior is the same, but I have not probed both thoroughly (only 1 so far has been probed).
When you review the schematics that I'm attaching, a few things to note:
-The pull-up for U21 is missing from the design, so that required 'blue-wiring' one to the board. The pull-up pulls up to 3.3V in order for its logic level to be compatible with the downstream AND gate which controls the XMOS reset signals. In scoping the board, I realized that one problem with this circuit is that the open-drain transistor on the output is not active until the supply that it is monitoring hits 700mV. Therefore, the reset signal was initially high when the core supply was coming up. This means that whenever the board is given the signal to power-up, the reset signal needs to be held low 'manually'. Even after taking action on this, the aforementioned problem persists.
-R51 turned out to be too big, due to the internal hysteresis of U13. It was replaced with a short. Now the supplies come up as expected.
-L11 and L12 are not 100 mOhm resistors as they appear in the schematic. Instead they are ferrite beads.
-Also, the component is labeled as XLF216-512-FB236, but the XEF part was placed on this board so that we could utilize the ethernet interface at a later time via an expansion connector.
Now, getting to the checklist that you graciously attached (thanks!):1.) The JTAG interface to the XCore has been disabled in the OTP security register.
If it has, it wasn't by me, as I've yet to be able to connect to the chip in order to manipulate any registers.2.) The device is being permanently held in reset by the RST_N signal.
Confirmed with a scope that this is not the case.3.) No clock is being supplied to the device; or the clock frequency supplied to the device is unsuitable for the selected PLL multiplier.
So the SI5351A on the board is behaving a little bit badly, in that the output frequency is not what I programmed (with the register values coming from the ClockBuilder Pro tool supplied by SiLabs). The intended output frequency is 25MHz, but instead the output frequency is 4.5MHz. Luckily, I broke out 0402 footprints for the mode pins so that I could adjust them as necessary in case something went bad. I placed 0-ohm resistors in those spots in order to set the mode to 0b00, which according to the datasheet should be correct for an input frequency of 4.5MHz. Still no luck with my issue.4.) The VDD core supply is outside of tolerance.
Core supply appears solid. ADP5310 is capable of providing 800mA.5.) The VDD PLL supply is outside of tolerance.
Filter was taken from reference design.6.) The power supplies have not been correctly sequenced.
Attached plot shows sequencing is correct, I believe.7.) The device, especially the ground paddle, has not been correctly soldered to the board.
BGA, so no ground paddle on this part. I can't speak to opens, but there are definitely no supply shorts.
So after some work this morning, I'm still in the same predicament I was yesterday :-(
Any more guidance would be appreciated.