I am (first) coding a task to handle a connection to an ADC (actual hardware wiring connection is about to happen in a couple of days):
LRCLK: from TP_21
MCLK: from TP_22
BCLK: from TP_20
i2s_DataIn: from expansion header X0D00: XS1_PORT_1A
I am also using the on-board DAC, which happens to use the same clock pins (except for MCLK, it uses MCLK_DAC). The on-board DAC uses the code from the example High Resolution Delay.
QUESTIONS:
(1) After I coded the "ADC Task" with an "i2s_master" hardware object, my task only enters into the main "while(1)" loop, but I get no "select" events. As mentioned before, there is no ADC connected yet, but I was expecting to see some "select" events since the XCore is the master of the bus. Am I missing something (code below)?
(2) Is the hardware connection scheme (i.e. sharing clocks) correct?, does the buffer (on board) have enough juice to drive both ADC and DAC (and DSP in the case of the shared MCLK) ?
...another piece of information: the ADC is configured by hardware connections (pins hi/low for master/slave mode, no i2c required).
...there is some missing code (i.e. the buffer swap interface and the creation of the ADC task).
Code: Select all
//-----------------------------------------------------------------
// i2s_handler() -- ADC
//-----------------------------------------------------------------
[[distributable]]
void i2s_handlerADC(server i2s_callback_if i2s, client interface BuffSwap, buffSwap, int initialBUff[])
{
int * movable AdcBuff = &initialBuff[0];
unsigned int adcDataCnt = 0;
while (1)
{
select
{
case i2s.init(i2s_config_t &?i2s_config, tdm_config_t &?tdm_config):
// Configure the I2S bus
i2s_config.mode = I2S_MODE_LEFT_JUSTIFIED;
i2s_config.mclk_bclk_ratio = (MASTER_CLK_FREQ/SAMPLE_FREQ)/64;
break;
case i2s.restart_check() -> i2s_restart_t restart:
// This application never restarts the I2S bus
restart = I2S_NO_RESTART;
break;
case i2s.receive(size_t index, int32_t sample):
AdcBuff[adcDataCnt] = sample;
if(++adcDataCnt == REC_SAMPLES)
{
buffSwap.BuffSwap(AdcBuff);
adcDataCnt = 0;
}
break;
case i2s.send(size_t channelIndex) -> int32_t sample:
sample = 0;
break;
}
}
}
Code: Select all
on tile[1]:
{
configure_clock_src(mclk, pMclkIn1);
start_clock(mclk);
i2s_master(xfaceI2sDac, pI2sDacDout, 1, null, 0, pBClk, pLRClk, bclk, mclk);
i2s_master(xfaceI2sAdc, null, 0, pi2sAdcDin, 1, pBClk, pLRClk, bclk, mclk);
}
on tile[1]: [[distribute]] i2c_master_single_port(xfaceI2c, 1, pI2cDac, 100, 0, 1, 0);
on tile[1]: [[distribute]] i2s_handlerDAC(xfaceI2sDac, xfaceI2c[0], BridgeToDac); // DAC
on tile[1]: [[distribute]] i2s_handlerADC(xfaceI2sAdc, swapAdcXface, AdcData1Buff); // ADC
on tie[1]: DummyTask(swapAdcXface, AdcData2Buff);