XE232 USB & XTAG

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davidk
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XE232 USB & XTAG

Post by davidk »

XMOS processor: XE232-1024
Migrating from XS1-G04B to XE232 processor.

USB
Q1) What is the correct hardware configuration of the un-used USB ports?
Reviewed available documentation but cannot locate how to configure the unused USB port connections.
The XE232 data sheet reference to "how to connect those USB ports are documented in an application note on USB for xCORE-200." leads to software centric app. notes.

xTAG Debug Connector
The XS-2 Evaluation Board ,with XS1-G04B, XTAG connector pin-out is different than what is identified on the XE216 evaluation boards and in the XE232 data sheet.
Referencing XE232 data sheet Section G.2 & G3. for full xSYS header.
Q2) Has there been a change to the xTAG debug connector pin out from the XS1-G04B to the XE232 processors?
Q3 UART connections of the XS-2 Eval. Bd. are missing from the XE216 Evaluation boards and XE232 data sheet is that correct?
Q4) Is the xTAG Pin3 TRST_N (MSEL) "Select boot from JTAG" signal not required for the XE2xx series?
Q5) Are there multiple versions of the XTAG debug board or just one for all Evaluation Boards?


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mon2
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Post by mon2 »

Hi.

A1) Review this port mapping chart:

https://www.xmos.com/search/content?term=X07017

If you do not use USB IP then cannot imagine the USB PHY performing its duty so you should be fine to leave the pins floating. Could park the USB D+ / D- pins with some PU / PD resistors if you really wish. Read that some will short D+ to D- for a similar disable on PCs. Still continue to power the USB rails as who knows where they end up inside the XMOS CPU. Would not want a portion of the XMOS CPU to be powered while other parts to be not = chaos city.

A2) Do not believe so but XMOS did start many moons ago using the FTDI USB devices but then migrated to use the XMOS CPU to kick up the debug support by many folds. Have you seen a difference in the pinout and/or tool schematics?

A3) Yes, from the hardware manual schematics, it appears that the UART pins of the XTAG XSYS connector are not supported with this XE216 Evaluation board. Unless the UART is of value to you, the debugging is over JTAG including the printf use so the debugging is not blocking. You can always manually wire up 2 free 1-bit GPIO pins of your choice onto the 2.54 mm IDC XSYS header for this MIA UART interface.

A4) Sounds correct since pin 3 of the XSYS connector is not connected to the XE216.

A5) XTAG-3 is the latest and current design used by XMOS for the the JTAG interface.

https://www.xmos.com/download/private/x ... 1.0%29.pdf
davidk
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Post by davidk »

Some what confused by provided I/O mapping spreadsheet. The data sheet states that the "TILE unused I/O is unaffected when either USB or Ethernet is employed.
The ORANGE and BLUE high-lighted I/O is consistent with data sheet identified I/O signals.
The Green high-lighted I/O is in question.
Reviewing TILE 1, with no USB but Ethernet employed, Pin Names X1D02-X1D09, X1D14-X1D21.
Q1) For these I/O pins the 16b(word) and 8b(byte) option are not available but can be used as four (4) 4b(nibble)?
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mon2
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Post by mon2 »

Q1) For these I/O pins the 16b(word) and 8b(byte) option are not available but can be used as four (4) 4b(nibble)?
Correct. XCORE-200 series is unique this way. Think of it as internal mux logic that permits some combinations to enable while others are disabled. If you select this combination, then yes, 4 x 4 Bit ports are available for your use. This is an improvement over the XS1 series of the CPU devices.

Reference:

http://www.xcore.com/viewtopic.php?f=7& ... rts#p20173
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