USB Audio Reference Design: change output format

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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kenmac
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Joined: Tue May 13, 2014 9:37 am

Re: USB Audio Reference Design: change output format

Postby kenmac » Tue Dec 02, 2014 6:07 pm

Core Audio in OSX can do some unexpected things with resampling. I am not sure if this is affecting you though. It is strange that you are seeing "extra bits" in the I2S stream. Are the MSBs of each channel slot as expected?
danielone
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Joined: Fri Nov 14, 2014 4:19 pm

Postby danielone » Thu Dec 04, 2014 12:17 pm

Hi Kenmac,

After your feedback I made a try yesterday evening: to avoid Core Audio performing the resampling.

And you are right: I took a 16/44.1 file, I open it in Audacity (freeware wave editor) and I resampled it to 24/96. Then, if, in the audio settings panel, you choose 24/96, the file is correctly output with the 8 padded leading zeros:

24bitres.jpg
(283.49 KiB) Not downloaded yet
24bitres.jpg
(283.49 KiB) Not downloaded yet


If you set in the control panel other resolutions / sampling frequencies, then Core Audio will do the resampling and the output is messed up:

24bit.jpg
(282.19 KiB) Not downloaded yet
24bit.jpg
(282.19 KiB) Not downloaded yet


Please note that, if resampled by core audio, you neither see the 8 padded zeros that are hardcoded. This is puzzling me very much.

I would like to hear also Ross opinion about this.

Best regards.
dweeb4
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Joined: Mon Jan 19, 2015 12:47 pm

Postby dweeb4 » Sat Feb 11, 2017 12:03 am

I know this is an old thread & I hope people don't mind me resurrecting it but I'm currenty trying to get to grips with the bit masking used in this clocking

I think I have a handle on BCLK bit masking - it defines the clock cycle of BCLK in relation to MCLK clock cycle of ?
As the XMOS dcomentation states
The bit clock is generated by performing outputs of a particular pattern to p_bclk to toggle the output at the desired rate. The pattern depends on the divide between MCLK and BCLK. The following table shows the pattern for different values of this divide:

Divide Output pattern Outputs per sample
2 0xAAAAAAAA 2
4 0xCCCCCCCC 4
8 0xF0F0F0F0 8

In other words a divide 8 uses the bit mask 0xF0F0F0F0 or the bit pattern (1111 0000 1111 0000 1111 0000 1111 0000)
If I understand this correctly this BCLK will be high for 4 MCLK clock cycles, then low for 4 MCLK clock cycles, etc.

Divide by 4 gives this bit pattern 1100 1100 1100 1100 1100 1100 1100 1100 or BCLK high for 2 MCLK clock cycles, low for 2 MCLK clock cycles, etc

LRCLK bit masking is just a set bit allocation:
For I2S 0x7fffffff followed by 0x80000000 - both repeated
For RJ 0xffffffff followed by 0x00000000 -repeated

The requirement in this thread was to code for 24 bit RJ sample output - does this not require:
0xFFFFFF & 0x000000 bit patterns for LRCLK
BUT also changing the loops in audio.xc from 32 to 24?

Edit: Is the following code correct (& what's the function of @ tmp)? :
p_lrclk @ tmp <: 0xFFFFFF00; /* 24 bit in 32 bit frame LJ bit-mask ?? */
p_lrclk @ tmp <: 0x00FFFFFF; /* 24 bit in 32 bit frame RJ bit-mask ?? */

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