Anyone else working on a multi-channel over USB design?

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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dizengoff
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Anyone else working on a multi-channel over USB design?

Post by dizengoff »

I can't seem to find any solid information about how much I/O count is possible with the LS2? Or should I be looking at the G instead? 16x16 would be nice. Should I bother posting this here? Previous similar posts seem to go unanswered...


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lilltroll
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Post by lilltroll »

Check Chapter 5 for general resource usage
https://www.xmos.com/download/public/US ... 2.0%29.pdf

and

Check Chapter 2.11 regarding ULPI on L devices
https://www.xmos.com/download/public/XS ... 77C%29.pdf

You will need many 1 port pins if you are using a I2S CODEC, so you need to look for port with the naming convention
1PCAPITAL
on page 5 here
https://www.xmos.com/download/public/XS ... 66H%29.pdf

and on page 4... here
https://www.xmos.com/download/public/XS ... 66H%29.pdf

For each stereo channel, you will need a free 1 port pin, and you will also need free 1 bit ports for a MasterClock, a BitClock and a LeftRight Clock using I2S, and all CODECs as slaves.

Depending on the fs and channel count expected you also need to consider the MIPS usages in the threads, specially the USB threads.
dizengoff
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Post by dizengoff »

Thanks so much, it's greatly appreciated. I know delta sigma and clocking architecture very well, embedded design not so much.
For each stereo channel, you will need a free 1 port pin, and you will also need free 1 bit ports for a MasterClock, a BitClock and a LeftRight Clock using I2S, and all CODECs as slaves.
For a multichannel system I'd assume it's no different than any other setup--all converters in slave mode, one MCLK line, one BCLK line, and then one I2S line per converter I'd assume.
Depending on the fs and channel count expected you also need to consider the MIPS usages in the threads, specially the USB threads.
There's my question, ultimately. I've got the multi-channel eval board coming (should be here Wednesday). Is the L2 powerful enough to handle 16 channels of I/O at 192kHz or should I be looking at the quad core chip?

Is it possible to code these chips to handle I2C functions as well, such as A/D reset timing etc?

Maybe I should post an add in the jobs section :D.
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lilltroll
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Post by lilltroll »

One core has 16 1 bit ports, but on some chips not all ports are wired out.
One thread running @ 100 MHz can easily* serve 6 in and 8 out channels over I2S to a Cirrus CODEC, but that is as far I have tested, but the port timing is "easy" to simulate in the simulator.

I do not know the maximum channels for the USB thread. You might consider to use the new 700 MHz chip as the USB decoder if it is tight, serving an extra L2 chip with 16 in channels on core 0 and 16 out channels on core 1. One core doesn't have enough ports for 32 channels anyway, ( MCLK must be feed to each core externally, feeding the port logic of each core. )

There is a channel count vs MIPS for AVB over Ethernet in the documentation, but that is a rather different setup regarding MIPS (I believe)

*I did have time for IIR filters in the same thread as well.

I would test to emulate 16 in and 16 out by making a loopback in the code, just to test the USB, both on the OS side and the XMOS side.
dizengoff
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Post by dizengoff »

I do not know the maximum channels for the USB thread. You might consider to use the new 700 MHz chip as the USB decoder if it is tight, serving an extra L2 chip with 16 in channels on core 0 and 16 out channels on core 1
This is what I suspect, the XS1-G would be a better fit.

Another question: can these devices be aggregated on a USB bus to increase channel count?
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