USB Audio Reference Design: change output format

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
danielone
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USB Audio Reference Design: change output format

Post by danielone »

Hi all,

In order to suit the USB Audio Reference Design to my needs I need to perform two step of modification on the output:

tier 1: change from I2S to Right-Justified

tier 2: address two ports that outputs audio data at the same time for each channel in RJ format
port 1: right data RJ format
port 2: left data RJ format
port 3: BCK
port 4: latch enable

Tier 2 in order do directly interface XMOS uC with two BB PCM1704 DACs.

http://www.ti.com/lit/ds/symlink/pcm1704.pdf

I just ask if someone had the same necessity and/or is it possible to have just an input on how to do. Modifying an existing code is always a very much time-consuming process

Many thanks in advance.


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kenmac
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Post by kenmac »

You can modify the main audio loop in module_usb_audio::audio.xc

The I2S/Right Justified format is determined by a couple of lines that look like this:

p_lrclk <: 0x7FFFFFFF;
p_lrclk <: 0x80000000;

The hex value creates the offset through the MSB being 0111b or 1000b. You can see the transition from low to high/high to low and move it left or right by 1 bit.

I am not sure exactly what you mean for your "tier 2" modifications, but this should help you with right-justified.
danielone
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Joined: Fri Nov 14, 2014 4:19 pm

Post by danielone »

Hi kenmac, and thanks for your valuable help.

I will check your suggestion. I2S is a LJ format, so I think a right bitshift will be implemented in order to right-justify. PCM1704 only considers the last 24 bits in a 32 bit frame.

"tier 2" simply refer to a further step after obtaining a RJ output stream.
With RJ output stream I have to employ some latch register IC in order to divide the right and left channel due to PCM1704 being a mono dac.

My goal is implementing the channel split into the software stack. I should have 4 output ports on the xmos ic that output:

pin 1) right channel data rj
pin 2) left channel data rj
pin 3) bit clock
pin 4) latch register (high, pulsed down after LSB in order to push data through the DAC)

(basically it is a function performed by BB DF1706 but I want no interpolation nor oversampling)

Thanks.
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Ross
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Location: Bristol, UK

Post by Ross »

Do you want this format at the same time as I2S or instead of I2S?

Seems pretty similar to the DSD code, in that there is one port/line per channel - I would take a quick peek at that.
danielone
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Post by danielone »

Hi Ross,

I need this format instead of I2S

Thanks
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kenmac
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Post by kenmac »

It shouldn't be too difficult to adjust the audio loop to only 1 channel to each pin, using a similar technique to what I suggested for right-justified.

You can control the frequency/duty cycle of the LR clock via the writes I mentioned. Device to host channel transfers look like:

samplesIn[0] = bitrev(sample);

and host to device look like:

p_i2s_dac[0] <: bitrev(samplesOut[0]);

You can change the BCLK using 32 bit patterns like the LRCLK like so (this will allow you to divide the MCLK):

p_bclk <: 0xF0F0F0F0;

Modifying the audio loop like this for your use case would take you to something that looks a bit like the DSD code Ross mentioned.
danielone
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Post by danielone »

Hi all,

I performed some tests and I am quite confused.

First of all I compiled the 16b2 - 24b3 - 32b4 version of the software. This because if I am able to obtain a 24 bit sample in a 24 bit frame I need no justification.

Then, connecting to my Mac, I select the sample resolution but for 16,24 and 32 but the subframe size is always 32 bit. Aside of this, when 16 bit resolution is selected, I currently see some trailing zeros (hardcoded?) and it is correct.
16bit.jpg
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16bit.jpg
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But, if I select 24 bit I expect to find the bits from 25 to 32 set to zero but it does not happen. In the image below you can see that some data exceeds the 24 bit long
24bit.jpg
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24bit.jpg
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Further images from the 24 bit seen on the oscilloscope.
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4.png
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My question is: how is it possible to have 24 bits of data in a 24 bit frame (removing the delayed BCK pulse required by I2S interface that would be a 25th bit). Changing the makefile settings I have not been able to obtain this.

many thanks
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kenmac
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Post by kenmac »

You won't be able to configure 24bit in24bit frames from the Makefile. This is something you would need to code manually. The method I described in the previous post can be used for this too. I am not sure why your scope captures look like that though.
danielone
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Joined: Fri Nov 14, 2014 4:19 pm

Post by danielone »

Hi Kenmac,

I wonder, at this point, what does the 4.5.1 section in the USB Audio Design Guide means where it says: "Other values can be used (currently 4, 3 and 2 are supported by the design)." PS. http://www.usb.org/developers/devclass_ ... _final.zip in foot note is a dead link.

Aside of this do you figure why 24 bit samples have data in the 25-32 bit range? (My scope and logic analyzer shows some ones in this range, I supposed to find some hardcoded zeroes as in 16 bit setting)

Regards

D.
danielone
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Posts: 11
Joined: Fri Nov 14, 2014 4:19 pm

Post by danielone »

Hi all,

I managed to right justify the 24 bit sample format shifting the LR clock 8 bits right:

Code: Select all

#ifndef CODEC_MASTER
            
            p_lrclk <: 0xFFFFFF;
            doI2SClocks(divide);

#endif
and

Code: Select all

#ifndef CODEC_MASTER
            p_lrclk <: 0xFF000000;
            doI2SClocks(divide);
#endif
Now, the strange thing is that on MacOS 10.10, despite selecting in audio settings 24 bit format it seems that the data are 32 bits
24bit.jpg
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24bit.jpg
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In Windows XP with the Thesycon driver, data seem correctly formatted at 24 bits and right-aligned
24 bit win.jpg
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24 bit win.jpg
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Can someone explain what is wrong with MacOS?

Many thanks
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