JTAG for a chained XMOS XS-LSA-128

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WiFi
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Posts: 4
Joined: Wed Nov 23, 2016 10:35 am

JTAG for a chained XMOS XS-LSA-128

Post by WiFi »

I need some help for connecting the JTAG for a chained XMOS XS-LSA-128

Please check the attached schematic whether the connectinons and the logic will work for the chained XMOS XS_LSA-128

I cant get a stable start-up function in the excecuted design.

Massage:
.gbinit: No such file or directory.
auto-solib-add on
Undefined command_ "auto-solib-add". Try help".
connect adapter-id jIHd4MH5
Cannot connect, device is in use by another process
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PIXMOS.xn
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PIXMOS.xn
(5.22 KiB) Downloaded 289 times
XMOS JTAG Connect Link. R2.jpg
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XMOS JTAG Connect Link. R2.jpg
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mon2
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Post by mon2 »

Review the following xn file (for chaining 2 SliceKits) against yours for this project:

http://www.xcore.com/forum/viewtopic.php?f=47&t=3838

============

Why are the MISO pins floating on the SPI flash devices ?

MISO = Master In, Slave Out in the SPI spec. That is, this pin is required to mate with the XMOS CPU else the CPU will not be able to read the contents from the respective flash device(s). The MISO pins must connect to a XMOS CPU.
WiFi
Junior Member
Posts: 4
Joined: Wed Nov 23, 2016 10:35 am

Post by WiFi »

thank you for your support on this topic.

the xn-file is tested and works with 2 chained slice kits with out problem

the SPI port is connected via the schematic harness X_SPI (see schematic)
to
S_Clk >L0X0D10
SPI MISO > L0X0D0
SPI MOSI > L0X0D11
CS B > L0X0D1
CS ST > L0X0D23

additional info:
after PWR-ON it's possible to start the JTAG without failure
- all cores are running
if you start JTAG again it doesn't work anymore
is something wrong with Debug_N or MSEL_IN

but it's not possible to flash the boot SPI (U210)
henk
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Posts: 347
Joined: Wed Jan 27, 2016 5:21 pm

Post by henk »

Hi,

a few comments:

1) I don't see a power-on-reset circuit - is that somewhere else? You will need one.

2) U212 has one init tied high - the other tied to RST_N; you may need both buffers to drive RST_N and TRST_N of two XS2-L16A devices. It don't think it is useful to tie the two outputs together, but not tie the two inputs together. I would tie pin 1 and 3 together to get some more drive strength.

3) the 10K pull-up on U212 may not be enough to pull all up - you could replace U212 with a driving buffer, and make sure the inputs are connected together. I would have two separate nets to the two xCORE chips to make sure that their resets get pulled down properly. See also section F of the data sheet.

4) U221 and U222 both buffer TRST_N and are then tied together.

5) U222 drives MSEL_in, but this can also be grounded by a jumper which seems unhealthy; it would put a lot of stress on U222

6) The error message from XGDB just means that some old XGDB process is hanging - kill that and try again.

Cheers,
Henk
WiFi
Junior Member
Posts: 4
Joined: Wed Nov 23, 2016 10:35 am

Post by WiFi »

Hi Henk,

thanks for your comments

Mode setting
When using the XMOS in the JTAG mode with link B for connecting Master U200 and Slave U201
is it then possible to make a hard wire setting for the Mode pin's
MODE [3:2] 00 on the master
MODE [3:2] 10 on the slave
Or is a dynamic MSEL Signal given from the XTAG2 necessary.

DEBUG
The function of Debug_N is not clear for me, when using two XMOS XS1-L16A-128 (Master Slave Mode)
Is DEBUG_N an Input for the XTAG2 module?

Is a buffer needed between Master and Slave .
In my actual PCB design there is no possibility to do this.

RESET
the RST_N (B8) and TRST_N (B13) are tied together and connected to the Output a CMOS Switch a SN74lvc1g3157 to get low impedance to GND when Reset is low active.


1) I don't see a power-on-reset circuit - is that somewhere else? You will need one.

There is a PWR and RESET Sequencer not shown on this schematic


Cheers,

Willi
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XMOS JTAG Connect LinkR3 20161215.jpg
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XMOS JTAG Connect LinkR3 20161215.jpg
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