Xcore200 Explorer kit with standard mii and 100 Mbit

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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hegt
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Posts: 19
Joined: Wed Sep 17, 2014 1:20 pm
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Xcore200 Explorer kit with standard mii and 100 Mbit

Post by hegt »

Hello,

I am trying to get the xcore 200 explorer kit running with the mii_ethernet_mac component.
The reason is that we could save a lot of cores when running only on 100 MBit if Gigabit support is not used.

My port configuration looks like this:

Code: Select all

port p_smi_mdio   = on tile[1]: XS1_PORT_1C;
port p_smi_mdc    = on tile[1]: XS1_PORT_1D;
port p_eth_reset  = on tile[1]: XS1_PORT_1N;

port p_eth_rxclk  = on tile[1]: XS1_PORT_1O;//XS1_PORT_1O;
port p_eth_rxd    = on tile[1]: XS1_PORT_8A;//8A
port p_eth_txd    = on tile[1]: XS1_PORT_8B;//?
port p_eth_rxdv   = on tile[1]: XS1_PORT_1B;
port p_eth_txen   = on tile[1]: XS1_PORT_1F;//1L
port p_eth_txclk  = on tile[1]: XS1_PORT_1G;
port p_eth_rxerr  = on tile[1]: XS1_PORT_1A;
port p_eth_dummy  = on tile[1]: XS1_PORT_8C;//?
clock eth_rxclk   = on tile[1]: XS1_CLKBLK_1;
clock eth_txclk   = on tile[1]: XS1_CLKBLK_2;
then I try to start an xtcp server with the following code:

Code: Select all

        /*---------------100 MBit ETHERNET----------------------------------------------------------*/
        on tile[1]: mii_ethernet_mac(i_eth_cfg, NUM_CFG_CLIENTS,
                                     i_eth_rx, NUM_ETH_CLIENTS,
                                     i_eth_tx, NUM_ETH_CLIENTS,
                                     p_eth_rxclk, p_eth_rxerr,
                                     p_eth_rxd, p_eth_rxdv,
                                     p_eth_txclk, p_eth_txen, p_eth_txd,
                                     p_eth_dummy,
                                     eth_rxclk, eth_txclk,
                                     ETH_RX_BUFFER_SIZE_WORDS);

        on tile[1]: ar8035_phy_driver(i_smi, i_eth_cfg[CFG_TO_PHY_DRIVER]);
        on tile[1]: smi(i_smi, p_smi_mdio, p_smi_mdc);


/*---------------GIGABIT ETHERNET----------------------------------------------------------*/
//        on tile[1]: rgmii_ethernet_mac(i_eth_rx, NUM_ETH_CLIENTS, i_eth_tx, NUM_ETH_CLIENTS,
//                null, null,
//                c_rgmii_cfg, rgmii_ports,
//                ETHERNET_DISABLE_SHAPER);
//        on tile[1].core[0]: rgmii_ethernet_mac_config(i_eth_cfg, NUM_CFG_CLIENTS, c_rgmii_cfg);
//        on tile[1].core[0]: ar8035_phy_driver(i_smi, i_eth_cfg[CFG_TO_PHY_DRIVER]);
//        on tile[1]: smi(i_smi, p_smi_mdio, p_smi_mdc);
/*---------------GIGABIT ETHERNET----------------------------------------------------------*/


        on tile[0]: xtcp(c_xtcp,
                1,
                null,
                i_eth_cfg[CFG_TO_ICMP],
                i_eth_rx[ETH_TO_ICMP],
                i_eth_tx[ETH_TO_ICMP],
                null,
                ETHERNET_SMI_PHY_ADDRESS,
                null,
                otp_ports,
                ipconfig);



The code is compiling and with the rgmii everything works fine. I am wondering if I have some ports wrong or if its just not possible to run the mii like this?


henk
Respected Member
Posts: 347
Joined: Wed Jan 27, 2016 5:21 pm

Post by henk »

Hi hegt,

To use the MII code you will need an MII PHY.

There isn't one on the exploder board,
so unless you have soldered one on
the extension headers it won't work.

Cheers
Henk
hegt
Member++
Posts: 19
Joined: Wed Sep 17, 2014 1:20 pm
Contact:

Post by hegt »

Allright, thanks...

Is there any possibility to reduce the used cores for the Gigabit Ethernet implementation?
henk
Respected Member
Posts: 347
Joined: Wed Jan 27, 2016 5:21 pm

Post by henk »

If you never go faster than 100 Mbit you can probably reduce the number of logical cores substantially. At a guess, you will still need the two tasks that talk to the RGMII PHY (that is two of them) that occupy two logical cores. For the other 6 tasks, you may well find you can reduce that because the data rate has come down by a factor 10. You may be able to combine them on, say, 2 logical cores.

Maybe somebody has looked into that?
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