XU208 resulting in noise when play PCM 705.6KHz/768KHz

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
Kula
Junior Member
Posts: 4
Joined: Fri Jul 21, 2017 9:26 am

XU208 resulting in noise when play PCM 705.6KHz/768KHz

Postby Kula » Wed Aug 02, 2017 9:10 am

Hi all,

I have a following experience with XU208 using Foobar 2000 to play PCM 705.6K/PCM 768K resulting in noise presenting during playback.
The rest of sample rates can be play without any problem nor noise.

I have configure the firmware for customfdefins.h:
/* Master clock defines (in Hz) */
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */

/* Maximum frequency device runs at */
#ifndef MAX_FREQ
#define MAX_FREQ (768000)

External audio clock changes to 45.1584MHz and 49.152MHz.

First of all, I have using Audio Precision to make sure the ES9028Q2M and AK4490 can successfully decode PCM 738KHz without any performance issue.
When play 1KHz 0dB sine wave, using Oscilloscope for measuring DAC's analog output, I find out that when Thesycon control panel or Mac book MIDI out set to 2 channels 16 bits, the measurement result in noise in the 1Khz sine wave.
However, if sets to 2 channels 24bits, the measurement is a strange wave, definitely not sine wave.
And when measuring with PCM 705.6KHz / 768KHz the I2S DATA / BCLK Jitter is really large.

Has anyone also experience with problem?
Or has anyone know any solution to solve this?

Thank you so much in advance and any help is greatly appreciated.

Best regards
Terry Lin
User avatar
infiniteimprobability
XCore Expert
Posts: 885
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Mon Aug 07, 2017 9:36 am

Hi, 768kHz is a pretty high rate (and not tested as part of the ref design) but I think it should be possible, especially on xcore 200 where the bit clock is generated in hardware. It might take some tweaks but the I2S inner loop is 1.3us and that should be enough to generate the DAC data, LR clock and sample transfer. Also, the data rate at 24b (32b) is 49.152Mbps which is within the ISO endpoint limit. So it feels feasible.

Is your xcore I2S master?

Can you report what happens to the LR clock period?

My suspicion is the I2S inner loop timing is being compromised somehow. Normally this results in the LR clock period being stretched.. Let me know and I'll suggest some work arounds.


<Edit>
One quick thing you can do to test to see if the communication with the buffer is pushing timing out is setting:

Code: Select all

#define MIXER  1
#define MAX_MIX_COUNT 0


This inserts a core in between audio/buffer which hides latency
Kula
Junior Member
Posts: 4
Joined: Fri Jul 21, 2017 9:26 am

Postby Kula » Thu Aug 10, 2017 2:11 am

XU208 I2S is master

During normal I2S data, the MSB is at the second BCK position after LRCK edge appears.
But what I discover is that during 768KHz, MSB is at the third BCK position after LRCK edge appears.

thank you in advance.
User avatar
infiniteimprobability
XCore Expert
Posts: 885
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Thu Aug 10, 2017 3:52 pm

That's helpful information. Does it stay like this for ever and not slip over time? If so it suggests a start up timing issue. Because the xcore is master, all timing is synchrnonous to it. SO the answer will likely lie in

Code: Select all

static inline void InitPorts(unsigned divide)


Can you let me know what the effect of enabling mixer is in your situation?
Also, please confirm your reference design version.
Thanks
Kula
Junior Member
Posts: 4
Joined: Fri Jul 21, 2017 9:26 am

Postby Kula » Fri Aug 11, 2017 6:53 am

Thank you so much for the tips.
I guess i will go do another double check for the firmware again.
User avatar
infiniteimprobability
XCore Expert
Posts: 885
Joined: Thu May 27, 2010 10:08 am
Contact:

Postby infiniteimprobability » Fri Aug 11, 2017 9:30 am

Can you answer the questions:
Does it stay like this for ever and not slip over time?
Can you let me know what the effect of enabling mixer is in your situation?

I may be able to provide some more detail about how to debug this if I know the answer to these!
Thanks
Kula
Junior Member
Posts: 4
Joined: Fri Jul 21, 2017 9:26 am

Postby Kula » Wed Oct 25, 2017 4:58 am

Hi,

I am using XMOS reference firmware 6.12.5 and 6.15.2 version, both are having DSD DCLK output having incorrect frequency issue after playing and stop DSD file using Foobar2000.

I found out that when using Foobar 2000, first playing PCM file and then playing DSD file and press STOP. DSD DCLK will outputting half of the PCM I2S BCK frequency.
For instance, if I played PCM 384KHz, I2S BCK frequency is 24.576MHz, then playing DSD file and STOP, DSD DCLK will be measured to 12.288MHZ.

Any idea how to solve this?

Thanks and best regards
dengzicheng
New User
Posts: 2
Joined: Sat Mar 12, 2016 10:08 am

Postby dengzicheng » Mon Dec 11, 2017 6:45 pm

@infiniteimprobability,I want to support 768KHz,I did this.
#define MIXER 1
#define MAX_MIX_COUNT 0

Sound like normal. But is this correct? Will it create any other problems?

I do not understand this sentence very well.
“This inserts a core in between audio/buffer which hides latency”

Return to “Applications”

Who is online

Users browsing this forum: No registered users and 11 guests