I2S slave & clock recovery
Posted: Fri Aug 04, 2017 5:37 am
Hi,
We have been trying to use the I2S_slave module from the lib_I2S in conjunction with clockgen.xc to implement a I2S slave PLL clock locked to the I2S clock.
We did so by in effect replacing ADAT by I2S in clockgen and defining an I2S_RX function based on SPDIF_RX with the relevant callback interface service routines, based on the lib_I2S documentation.
Documentation for clockgen is sadly worse than non-existent, as it's existence is barely acknowledged in the USB Audio documentation, yet is such a crucial component for SPDIF/ADAT and in our case I2S slave.
Unfortunately we seem have a few issues that cause our system to work incorrectly, specifically I2S data appears to be "loosing samples" causing input from I2S running at lower rates than the same SPDIF Signal sourced from the same signal source. We have manually verified the clock rates of BCK & WCK applied to XMOS to be correct and we can directly connect a ESS DAC Chip with internal ASRC to this I2S source and correctly decode the I2S signal to audio.
We are a bit snookered where to look and how to bets approach the rouble shooting. If anyone happens to have a working example of I2S slave with clock recovery vial C2100 PLL it would help a lot.
Greez SSAL
We have been trying to use the I2S_slave module from the lib_I2S in conjunction with clockgen.xc to implement a I2S slave PLL clock locked to the I2S clock.
We did so by in effect replacing ADAT by I2S in clockgen and defining an I2S_RX function based on SPDIF_RX with the relevant callback interface service routines, based on the lib_I2S documentation.
Documentation for clockgen is sadly worse than non-existent, as it's existence is barely acknowledged in the USB Audio documentation, yet is such a crucial component for SPDIF/ADAT and in our case I2S slave.
Unfortunately we seem have a few issues that cause our system to work incorrectly, specifically I2S data appears to be "loosing samples" causing input from I2S running at lower rates than the same SPDIF Signal sourced from the same signal source. We have manually verified the clock rates of BCK & WCK applied to XMOS to be correct and we can directly connect a ESS DAC Chip with internal ASRC to this I2S source and correctly decode the I2S signal to audio.
We are a bit snookered where to look and how to bets approach the rouble shooting. If anyone happens to have a working example of I2S slave with clock recovery vial C2100 PLL it would help a lot.
Greez SSAL