Can i put multiple ADCs and DACs on different tile with xu224 or xu232

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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infiniteimprobability
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Re: Can i put multiple ADCs and DACs on different tile with xu224 or xu232

Postby infiniteimprobability » Tue Mar 06, 2018 11:47 am

In a TDM frame you typically send 8 data words per frame per line. So at 96kHz that's 8*96000 = 768K long words per second (24.576Mbps) for a 1b port, which is already supported in the sw. Now do that over a 4b port where you are discarding 3/4 bits and we have to write 3,072,000M long words per second (98Mbps), and include all of the zip/unzip calculations which you would need to interleave, buffering as well as transferring samples from the host, outputting FCLK etc.
It doesn't sound feasible to me..
susanyin0501
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Postby susanyin0501 » Fri Mar 16, 2018 7:14 am

Thanks for your reply, infiniteimprobability
I'm validating 16 ins and 16 outs I2S mode transmiting with 4b port based on your code, i'll tell you the reseult soon.
susanyin0501
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Postby susanyin0501 » Wed Apr 04, 2018 8:33 am

Hi infiniteimprobability
I'd validated 16 ins and 16 outs I2S mode transmiting with 4b port, it worked well, thanks for your support!
susanyin0501
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Postby susanyin0501 » Wed Apr 04, 2018 10:31 am

Hi infiniteimprobability
one more thing, in deliver( ), if i add many codes for TDM mode transmit process with 4b port. the LRCLK time will be longer, LRCLK frequency will be changed? thanks
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infiniteimprobability
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Postby infiniteimprobability » Wed Apr 04, 2018 11:02 am

I'd validated 16 ins and 16 outs I2S mode transmiting with 4b port, it worked well, thanks for your support!

That's good. It passed a simulator test bench and I know one other customer is successfully using a derivative of this in hardware, but an extra positive datapoint is always good to get.
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infiniteimprobability
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Postby infiniteimprobability » Wed Apr 04, 2018 11:03 am

in deliver( ), if i add many codes for TDM mode transmit process with 4b port. the LRCLK time will be longer, LRCLK frequency will be changed?


If you add any code at all in the inner loop I would expect it to break timing and naturally push out the loop time. This code is very close to the limit, hence why it needs a few more MIPS that usual and won't go to 16Ch at 192kHz.
susanyin0501
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Postby susanyin0501 » Fri Apr 06, 2018 9:43 am

infiniteimprobability

How to determine LRCLK frequency? there are different souce code in deliver( ) use your I2S mode with 4b port transmiting and TDM 8 or 16 channel mode of demo code, but LRCLK always 48k when playback 48k audio stream, and 44.k playbck 44.k audio stream. why ?

"If you add any code at all in the inner loop I would expect it to break timing and naturally push out the loop time"
what means?
break timing, whick timing ,where to set it?

and the following function setting will cause LRCLK frequency change ?
if i want to transmit TDM mode with 4b port, shall i change this funciton? How to do it?
would you please give me some documents about it? thanks!

static inline void InitPorts_4b_port(unsigned divide)
{
unsigned tmp;

/* Clear I2S port buffers */
clearbuf(p_lrclk);

for(int i = 0; i < I2S_WIRES_DAC; i++)
{
clearbuf(p_i2s_dac[i]);
}
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
clearbuf(p_i2s_adc[i]);
}

p_lrclk <: 0 @ tmp;
#define DELAY_START 100//Enough cycles to get to I2S inner loop
unsigned out_data_ports_delay = tmp + DELAY_START + 24; //+24 because 4b port empties 4x quicker than 1b port so delay 3/4 of lrclock cycle
unsigned in_data_ports_delay = out_data_ports_delay - 1 + 8; //-1 because we setup read for before clock. +8 because we want to lag reading by one word (and main loop blocks on in)

unsigned lr_port_delay = tmp + DELAY_START;
/* Since BCLK is free-running, setup outputs/inputs at a known point in the future */
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_DAC; i++)
{
p_i2s_dac[i] @ out_data_ports_delay <: 0;
}

p_lrclk @ lr_port_delay <: 0x7FFFFFFF;
#pragma loop unroll
for(int i = 0; i < I2S_WIRES_ADC; i++)
{
asm("setpt res[%0], %1"::"r"(p_i2s_adc[i]),"r"(in_data_ports_delay));
}
}

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