Add SRC into the USB Audio 2.0 Reference Software

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ffomich
Experienced Member
Posts: 96
Joined: Mon Sep 15, 2014 1:32 pm

Add SRC into the USB Audio 2.0 Reference Software

Postby ffomich » Fri Dec 01, 2017 11:36 am

Hi,
I try to add SRC to the S/PDIF input in the USB Audio 2.0 Reference Software.
For example I want to receive S/PDIF@44100 input while all board works at 96000.

Please correct me if I am wrong.
Reference Design clocking scheme is:

Code: Select all

S/PDIF input -> SpdifReceive() -> ClockGen() -> (data) -> audio()
                                            |-> (clock) -> output port -> PLL


In the firmware I can select Clock Source: Internal or S/PDIF input.
1. Clock source = S/PDIF input, S/PDIF data is valid
In this case ClockGen() extracts clock from the input digital stream and all board CLKs is sync to the S/PDIF input.

2. (Clock source = Internal) or (Clock source = S/PDIF input, S/PDIF data is NOT valid)
In this case ClockGen() outputs clock from the internal clock generator and all board CLKs is sync to the internal clock.

Now I try to add SRC between SpdifReceive() and ClockGen(). Question is what to use: SSRC or ASRC?

Code: Select all

S/PDIF input -> SpdifReceive() -> SRC() -> ClockGen() -> (data) -> audio()
                                                     |-> (clock) -> output port -> PLL


1. Clock source = S/PDIF input, S/PDIF data is valid
In this case I think I need to use SSRC because SpdifReceive and ClockGen are sync to the same clock.

2. (Clock source = Internal) or (Clock source = S/PDIF input, S/PDIF data is NOT valid)
In this case I think I need to use ASRC like in the example AN00231_ASRC_SPDIF_TO_DAC. SpdifReceive and ClockGen are sync to the diferent clock.

Is my reasoning correct?
akp
Experienced Member
Posts: 100
Joined: Thu Nov 26, 2015 11:47 pm

Postby akp » Fri Dec 01, 2017 1:16 pm

If the S/PDIF input is invalid why would you be applying sample rate conversion? It seems to me that the code is designed so that if you are using S/PDIF input the system master clock must be synchronized to the S/PDIF stream through the ClockGen controlling the PLL (i.e. clock source = S/PDIF input). It would probably be desirable to implement idea 2 (ASRC) if you want to output the audio to a DAC on your board, in this case ClockGen wouldn't need to drive a PLL I suppose if the ASRC can estimate the input clock frequency from the average data rate on a streaming channel.
ffomich
Experienced Member
Posts: 96
Joined: Mon Sep 15, 2014 1:32 pm

Postby ffomich » Fri Dec 01, 2017 3:14 pm

Hi akp,

you are right, I don't need SRC when S/PDIF stream is invalid. But in this case ClockGen() starts to output clock to PLL from internal source. So this mode is equal to the (Clock source = Internal) mode.

Thanks for idea to estimate the input clock frequency in the ASRC() not in the ClockGen(). I think Rate Manager from the AN00231_ASRC_SPDIF_TO_DAC example already do this.

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