How to determine LRCLK clock frequency

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
susanyin0501
Active Member
Posts: 41
Joined: Thu Apr 20, 2017 9:00 am

How to determine LRCLK clock frequency

Postby susanyin0501 » Wed Apr 04, 2018 9:11 am

where set LRCLK clock frequency in source code?

In deliver( )
{

#ifndef CODEC_MASTER
/* LR clock delayed by one clock, This is so MSB is output on the falling edge of BCLK
* after the falling edge on which LRCLK was toggled. (see I2S spec) */
/* Generate clocks LR Clock low - LEFT */
#ifdef I2S_MODE_TDM
p_lrclk <: 0x00000000;
#else
p_lrclk <: 0x80000000;

#endif

#pragma xta endpoint "i2s_output_l"

#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
index = 0;
#pragma loop unroll
/* Output "even" channel to DAC (i.e. left) */
for(int i = 0; i < I2S_CHANS_DAC; i+=I2S_CHANS_PER_FRAME)
{
p_i2s_dac[index++] <: bitrev(samplesOut[frameCount +i]);
}
#endif

#ifndef CODEC_MASTER
/* Clock out the LR Clock, the DAC data and Clock in the next sample into ADC */
doI2SClocks(divide);
#endif

.....

#ifndef CODEC_MASTER
#ifdef I2S_MODE_TDM
if(frameCount == (I2S_CHANS_PER_FRAME-2))
p_lrclk <: 0x80000000;
else
p_lrclk <: 0x00000000;
#else
p_lrclk <: 0x7FFFFFFF;
#endif
#endif

index = 0;
#pragma xta endpoint "i2s_output_r"
#if (I2S_CHANS_DAC != 0) && (NUM_USB_CHAN_OUT != 0)
/* Output "odd" channel to DAC (i.e. right) */
#pragma loop unroll
for(int i = 1; i < I2S_CHANS_DAC; i+=I2S_CHANS_PER_FRAME)
{
p_i2s_dac[index++] <: bitrev(samplesOut[frameCount + i]);
}
#endif

#ifndef CODEC_MASTER
doI2SClocks(divide);
#endif

....
}

Does LRCLK frequency set in this function? but if i add some source code in this function, LRCLK frequency will be change.

would you please tell me where set LRCLK frequency and how to determine LRCLK frequency? thanks very much!
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andrewxcav
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Posts: 60
Joined: Wed Feb 17, 2016 5:10 pm
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Postby andrewxcav » Thu Apr 05, 2018 2:05 pm

You should just be able to set up the appropriate struct in i2s.h. These configs are designed to do most of the work for you in terms of clocking ratios / edges.

Depending on what mode you choose the LRCLK will trigger differently (as you can see in the code that you posted here):

I2S_MODE_I2S, ///< The LR clock transitions ahead of the data by one bit clock.
I2S_MODE_LEFT_JUSTIFIED, ///< The LR clock and data are phase aligned.

In general, you should never need to modify any code in a library.
User avatar
Ross
XCore Expert
Posts: 768
Joined: Thu Dec 10, 2009 9:20 pm

Postby Ross » Mon Apr 09, 2018 5:30 pm

LR frequency in I2S is the sample rate frequency
susanyin0501
Active Member
Posts: 41
Joined: Thu Apr 20, 2017 9:00 am

Postby susanyin0501 » Wed Apr 11, 2018 8:11 am

Thanks for your reply, Ross and andrewxcav
susanyin0501
Active Member
Posts: 41
Joined: Thu Apr 20, 2017 9:00 am

Postby susanyin0501 » Mon May 07, 2018 12:21 pm

Does LRCLK frequency set in deliver( )?

if i add some source code in deliver( ), 5 in 5 out TDM16 mode, LRCLK will be less than 48K when playback 48K audio. please check add_code_in_deliver.xc
but i decrease some code in deliver( ), for example, i comment DAC process code, LRCLK will not be changed when playback 48K audio, still 48K, please refer to decrease_code_in_deliver.xc

why will LRCLK be changed when adding source code, but decrease code, LRCLK will not change ( following sample frequency) ?

would you please give some idea? thanks
Attachments
add_code_in_deliver.xc
(6.84 KiB) Downloaded 44 times
add_code_in_deliver.xc
(6.84 KiB) Downloaded 44 times
decrease_code_in_deliver.xc
(4.61 KiB) Downloaded 44 times
decrease_code_in_deliver.xc
(4.61 KiB) Downloaded 44 times

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