Min Power consumption for a UAC2 to I2S bridge?

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
janneb
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Min Power consumption for a UAC2 to I2S bridge?

Postby janneb » Sat Sep 22, 2018 12:49 pm

Hi,

Anyone here that's been doing some power profiling and happen to know what to expect in terms of power consumption for a usb device to i2s bridge setup, say 48k/24-bit stereo.

I haven't been using xmos myself (yet), but I guess with all peripherals off and scaling the cpu speed to what's needed, we could reach a pretty low power numbers!?


best J
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infiniteimprobability
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Postby infiniteimprobability » Tue Sep 25, 2018 7:58 am

It depends which chip you use. You need to be careful of scaling the chip speed because XUD (the USB driver) needs to still talk at nigh on 0.5Gbps (USB High speed). You can certainly get south of 400mW easily and even a fair bit below 300mW with some changes (milage varies according to system). Things like setting CHAN_BUFF_CTRL in the Makefile and reducing the switch speed help a lot:

Code: Select all

#include <xs1.h>
#define SWITCH_DIVIDER 0x10
write_sswitch_reg(get_local_tile_id() + 1, XS1_SSWITCH_CLK_DIVIDER_NUM, SWITCH_DIVIDER - 1);


This only works if you have a single tile or slow traffic between tiles.

Strangely I never measured a significant power change when changing between sample rates or bit depths..
janneb
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Postby janneb » Sat Sep 29, 2018 11:58 am

Thanks! Is it possible to somehow profile what parts of the code vs peripherals that's drawing current?
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infiniteimprobability
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Postby infiniteimprobability » Tue Oct 02, 2018 9:38 am

janneb wrote:Thanks! Is it possible to somehow profile what parts of the code vs peripherals that's drawing current?


Yes - we have done that and the above recommendations are as a result of the work. The main offender is the XUD task which talks to the PHY. It has to run at full tilt in all states because it talks to a 480Mbps PHY. The rest of the tasks are doing nothing most of the time (eg. I2S brief burst of activity each half I2S frame, and buffer manages some samples every SOF period).
The PHY uses a fairly fixed amount of power but that needs to be on the whole time. Of course just clocking a chip at 500MHz will also consume a base amount of power, but the cores are quite good about clock gaiting while they are waiting on an event.

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