"ASYNC" S/PDIF and clockgeneration

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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"ASYNC" S/PDIF and clockgeneration

Postby lilltroll » Sun Mar 25, 2012 10:41 pm

What is the latest code status on async S/PDIF including clockgeneration, e.g. The S/PDIF RX only extracts the data (as in the S/PDIF GitHUB code), thus doesn't try to recover a Masterclock (RMCLK) via an anlogue PLL.

What I can see there is at least 2 options for clockgeneration.
I may use a MasterClock (MCLK) from an crystal, and use digital resampling applied on the signal when the datarate from the S/PDIF are drifting from the MCLK. But this is not so trivial typ of resampling, but it could give really nice jitterattenuation.

An other option is to use a "Hybrid Analog-Digital Phase Locked Loop" where the digital input would come from the intrinsic Clock from the S/PDIF.

Is there any code examples when the XAI-board or MultiChannel USB card is used as a S/PDIF -> I2S -> DAC available.
Probably not the most confused programmer anymore on the XCORE forum.
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Postby Ross » Mon Mar 26, 2012 10:12 pm

The L2 USB Audio Reference Design uses an external fractional-n clock multiplier to generate the master clock from a reference clock generated by the XCore (based on the S/PDIF input stream)

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