Wi-Fi sliceCARD and ports on startKIT
Posted: Thu Dec 29, 2016 7:28 pm
Pins not found
In the examples I see where the Wi-Fi sliceCard is not used with the startKIT I see that
in Main.xc in app_tiwisl_simple_webserver. I have found no example with it running in the startKIT [1].
My problem is that I can't see that [4E0..4E3] or [X0D26,X0D27,X0D32,X0D33] are availaible on the Wi-Fi sliceCard. It's [4C0,4C1,4D0,4D1] or [X0D14,X0D15,X0D16,X0D17] that are available on PCIe [B6,B7,B9,B11]. See attached files for an overview.
What am I missing?
[1] http://www.xcore.com/forum/viewtopic.ph ... lit=WI+FI#
1-bit port in set of 32 bit port?
I think not: that a pin like X0D52 that only is mapped as part of XS1_PORT_32A [32A3] may be type cast into a 1-bit port? I'm sure they are hard wired? In other words I have to use standard bit handling?
Not touching other pins also defined in a bigger set
A last point: how do I make sure that this bit handling will not fiddle with the other bits that are not only mapped onto XS1_PORT_32A but also like XS1_PORT_4A or XS1_PORT_1E - in other modules? Is there a general scheme for modules that use some of the pins but not all? I have read the literature [2], [3] but probably missed the forest for the trees. (I also mention this question at "Atomicity of handling of port pins" at https://www.xcore.com/forum/viewtopic.php?f=26&t=5096)
Update 6Jan2017: I have discovered pin group "precedence". See https://www.xmos.com/support/tools/libr ... nent=14810. It solves my question.
[2] http://www.xmos.com/download/private/XS ... 1373A).pdf
[3] https://www.xmos.com/download/private/I ... 2738B).pdf
In the examples I see where the Wi-Fi sliceCard is not used with the startKIT I see that
Code: Select all
on tile[0]: wifi_tiwisl_ctrl_ports_t tiwisl_ctrl =
{
XS1_PORT_4E, // nCS - Bit0, Power enable - Bit1
XS1_PORT_1L, // nIRQ
};
My problem is that I can't see that [4E0..4E3] or [X0D26,X0D27,X0D32,X0D33] are availaible on the Wi-Fi sliceCard. It's [4C0,4C1,4D0,4D1] or [X0D14,X0D15,X0D16,X0D17] that are available on PCIe [B6,B7,B9,B11]. See attached files for an overview.
What am I missing?
[1] http://www.xcore.com/forum/viewtopic.ph ... lit=WI+FI#
1-bit port in set of 32 bit port?
I think not: that a pin like X0D52 that only is mapped as part of XS1_PORT_32A [32A3] may be type cast into a 1-bit port? I'm sure they are hard wired? In other words I have to use standard bit handling?
Not touching other pins also defined in a bigger set
A last point: how do I make sure that this bit handling will not fiddle with the other bits that are not only mapped onto XS1_PORT_32A but also like XS1_PORT_4A or XS1_PORT_1E - in other modules? Is there a general scheme for modules that use some of the pins but not all? I have read the literature [2], [3] but probably missed the forest for the trees. (I also mention this question at "Atomicity of handling of port pins" at https://www.xcore.com/forum/viewtopic.php?f=26&t=5096)
Update 6Jan2017: I have discovered pin group "precedence". See https://www.xmos.com/support/tools/libr ... nent=14810. It solves my question.
[2] http://www.xmos.com/download/private/XS ... 1373A).pdf
[3] https://www.xmos.com/download/private/I ... 2738B).pdf