concurrent I2C and I2S operation

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amninder
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concurrent I2C and I2S operation

Post by amninder »

Hi Guys ,

We are using XS1-U16A-128-FB217-C10 XMOS audio controller in our design to convert USB audio to I2S. However, we observed that any I2C transaction while audio playback would momentarily disrupt the audio being played. It looks like XMOS chip is not doing multi-tasking here.
I am using pins X1D00/X1D01 for I2C CLK/DATA and pins X1D11/X1D13/X1D22 for SDA/WS/SCLK on the chip.
My question is if XMOS is capable of handling I2C transactions without effecting the audio being played? If yes, is it a firmware change or it would need re-assignment of pins on the XMOS chip.

I would appreciate your quick response on this issue.
Thanks
Amninder


peter
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Post by peter »

The xCORE is explicitly designed to run multiple tasks in parallel tasks. If the I2C is interfering with the audio path then they are probably sharing the same logical core. Are you able to share you top-level main and how the tasks are assigned?

Peter
ahogen
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Post by ahogen »

Section 7.1 (page 13) of the datasheet for you part, and all the other XMOS parts I've encountered so far, says...
Each tile has 8 active logical cores, which issue instructions down a shared four-stage pipeline. Instructions from the active cores are issued round-robin. If up to four logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores).
So, because these cores have a shared pipeline, they really aren't all that independent. They don't even have some "smart" pipeline arbiter or anything, so the only thing really parallel about this is maybe queuing up instructions. It's the tiles that seem to be fully independent of each other and are therefore actually capable of running in parallel.

As far as why your I2C appears to be interfering with your I2S execution, I don't have an idea.
peter
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Post by peter »

The xCORE-200 has a 5-stage pipeline and each task can only consume a maximum of 1/5th of the machine's execution cycles. So, up to the point of having 5 tasks running they all are allocated 100MHz (no more) and are independent of each other. It is true that if you add more active tasks so that you have 6, 7 or 8 active tasks then the total 500MHz available is shared between the active tasks and so there is an impact of one task on the performance of another.

In terms of I2C and I2S interfering with each other, it will be down to how those two tasks have been coded. They need to be de-coupled such that they don't interfere. Without seeing some code for how the two tasks are connected it is impossible to say what is wrong.
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