Run Multichannel Audio Platform with 16kHz

[xaerox]

Hello everyone,
I'm trying to run the xCore-200MC Platform with 16kHz transfering Audio-Data via USB.
I just set the Default Frequency and Minimum Frequency to 16kHz.
The Master-Clock Frequency (24,576MHz) will be the same, so I don't have to change it.
I know, that it will work for the Audio I/O-Cores but I have no idea of the USB-Device and its Thesycon Driver for Windows.

Thank you for your answers.
Thomas

[xchips]

Hi, also add 16k in this array: audiorequests.xc->Line 877:

Code: Select all

unsigned lowSampleRateList[] = {8000, 11025, 12000, 16000, 22050, 24000, 32000};

and try again.

Regards.

[xaerox]

Thank you for your answer.
I can't find this line in my whole workspace.
Maybe I have an older revision version "sw_usb_audio-[sw]_6.15.2rc1"?

Kind Regards,
Thomas

[xaerox]

Sorry for double posts.
I found out, where the error starts. I set MIN_FREQ to 16000. DEFAULT_FREQ also is 16000.
So in the audio.xc file the MCLK/BCLK ratio will be:

Code: Select all

#define MAX_DIVIDE_48 (MCLK_48/MIN_FREQ_48/64)

which is the value 24.

The error is coming from these lines:

Code: Select all

#if (MAX_DIVIDE > 16)
#error MCLK/BCLK Ratio not supported!!
#endif

I understand why, because only MAX_DIVIDE up to 16 is aviable.

So I would try to expand these lines for up to 24-divide:

Code: Select all

#if (MAX_DIVIDE > 8)
             case 16:
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;

                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                break;
#endif
#if (MAX_DIVIDE > 4)
           case 8:
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                p_bclk <: 0xF0F0F0F0;
                break;
#endif
#if (MAX_DIVIDE > 2)
            case 4:
                p_bclk <: 0xCCCCCCCC;
                p_bclk <: 0xCCCCCCCC;
                p_bclk <: 0xCCCCCCCC;
                p_bclk <: 0xCCCCCCCC;
                break;
#endif
#if (MAX_DIVIDE > 1)
            case 2:
                p_bclk <: 0xAAAAAAAA;
                p_bclk <: 0xAAAAAAAA;
                break;
#endif
#if (MAX_DIVIDE > 0)
            case 1:
                break;
#endif

I would do something like:

Code: Select all

#if (MAX_DIVIDE > 16)
             case 16:
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;

                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;

                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                p_bclk <: 0xff00ff00;
                break;
#endif

*EDIT*
But maybe I have to do with different vaules for p_bclk.
will this be correct:

Code: Select all

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

?

Kind Regards.

[larry]

On xCORE-200 the switch statement with p_bclk outputs isn't used. Instead, bit clock is a hardware divided version of master clock, see audioports.xc:

Code: Select all

#if defined(__XS2A__)
    /* Clock bitclock clock block from master clock pin (divided) */
    configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
    configure_port_clock_output(p_bclk, clk_audio_bclk);
#else

Generating a 1.024MHz bit clock (64x16kHz) out of 24.576MHz should be possible with a divide value of 12 in the code above, but there might be other places in the code where it assumes a power of two. It might be best to try first and see.

[xaerox]

Thank you for your answer.
I can't find these lines to change the bitclock-frequency.
In my replies before, I told about defining new BCLK Outs for a MAXDIVIDE = 24.
On my oscilloscope I can watch differences of my bclk-signal. The LRCLK is very good. It shows me the 16kHz Signal. My computer also recognize the Platform with an 16kHz Device and I can run it in Audacity. The Problem is, that I can't receive any Audio Waveforms, because the BCLK doesn't have an stable frequency (the periodes haves different lengths). Thats Why the ADCs couldn't transfer Audio via I2S.
One more information. It's not really the Multichannel audio-platform. It's an own board with fixed Masterclock (24,576 MHz). But the schematic is very similar to the Audio-Platform from XMOS.
I think this codes does any troubles in my bclk-signal:

Code: Select all

case:24
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

This is for the devide 24, so I send out 32-bit hexadecimal, where I send three 4-Bit signals in one line (fff-000-fff.....).
Can someone see an mistake in this code? So my bclk signal looks like (1= high, 0=low):

0110000101110100010111

kind regards,
thomas

[Ross]

is your board using XS1 or xCORE-200 (XS2)?

[xaerox]

@Ross: It's an XS2 device.
To everyone: I downloaded and modified the new XMOS Firmware for the XMOS-Multichannel Audio Platform.
So now I can see via the USB Audio Control Panel, that the device works with 16kHz. The Problem I have is, that I can't record my 16 channels.
Using the Windows 7 audio-settings I can see, that the device could work with 16 kHz in 16-bit format. So I think the USB-Packet-Size ist 24-Bit. Am I right?
Am I'm right, the the problem currently is the Windows 7 WASAPI - codec?
Is it possible to send USB-packets with 16-Bit resolution?

Sorry for my bad english, I hope you understand my problem.

kind regards,
Thomas

[xaerox]

Hello everybody,
after a short break I'm trying out to solve the problem using the xmos board with 16 kHz Audio-Interface.
I tried to chance every comment above but I can't run this device on my computer.
@larry:
This code is marked as grey, which means that __XS2A__ is not defined.

Code: Select all

#if defined(__XS2A__)
    /* Clock bitclock clock block from master clock pin (divided) */
    configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
    configure_port_clock_output(p_bclk, clk_audio_bclk);
#else

I changed in audio.xc about lines 127....

Code: Select all

case:24
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;
p_bclk <: 0xfff000ff;
p_bclk <: 0xf000fff0;
p_bclk <: 0x00fff000;

in order to get the bitclock correctly.
If I calculate:
MCLK = 24.576 MHz;
FS = 16000;
MAXDIVIDE = MCLK/FS/64 = 24
So That means I need to generate the Bit-Signal with the code scheme above. Would you agree with me?
I just want to run this device on windows or linux with 8 channel 16 kHz / 24 Bit.
Or is it possible with 16 Bit?

thank you.
best regards
thomas

[larry]

Because it's an XS2 chip, __XS2A__ will be defined and the p_bclk outputs will be excluded

Unfortunately the xTIMEcomposer projects don't have __XS2A__ set, so it thinks it isn't defined and greys out the wrong section

As a workaround, you can set __XS2A__ in xTIMEcomposer. To do that, open properties of the module_usb_audio project and go to C/C++ General, Paths and Symbols, and click Add on the Symbols tab. The set __XS2A__ to 1. Eclipse will rebuild its code structure index and grey out the correct section