Understanding port mappings

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jorsc
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Understanding port mappings

Post by jorsc »

I'm trying to understand how port mappings work with xcore.
I'm reading a document https://www.xmos.com/download/private/X ... 38A%29.pdf.
In the example:
on tile [0] : in port p = XS1_PORT_1A
uses the 1-bit port 1A on xCORE Tile 0, which is connected to pin X0D00.

My question: How do I know that XS1_PORT_1A is connected to X0D00 and where is this mapping described?

I've also looked in datasheets and in app examples (I'm using the multichannel audio board) to try to figure out how one can relate similar mapping with physical pins and can't figure it out...


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mon2
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Post by mon2 »

Hi.

1) The multichannel audio board is based on the XCORE-200 CPU line so you have a more advanced device than the earlier XS1 core. Please note this detail. However, your question is relevant to the XCORE-200 XMOS CPUs as well.

2) Review the table of port pins (Figure 1) and read from LEFT to RIGHT. If the port pin is mapped on the left in your code then the options on the right for the same port pin are no longer available for your use.

Say for example:

if you decide to use XnD36 as a single bit port with alias label 1M which could be XS1_PORT_1M in the XMOS pin header file then you can no longer use the alias port names to the right of the same pin (ie. 8 bit wide port (8D0), weight 0 is off the options for your use and so is the 16 bit port (16B8); weight 8).

The 1M alerts the reader that the pin will be accessed as a "1" bit port and the label is M.

The "n" in the port defines the Tile linking that port pin.

So in your post, X0D00 = X"0" = port pin in Tile # 0 and D00 = locate this pin on your physical device chart and access this as XS1_PORT_1A.

That is, if you output for example a 1 or 0 to XS1_PORT_1A then X0D00 on the physical pin will toggle accordingly.

Another example, let us say it is X1D00 then this means now you are dealing with a port pin on Tile # 1; X2D00 = port pin on Tile # 2, etc.

Hope this helps. Post back if you have other questions or if not clear. The details are bit funky to understand as XMOS is unique but logical (in a Spock voice) after some staring at the documentation.
jorsc
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Joined: Fri May 05, 2017 1:39 pm

Post by jorsc »

Thanks for a very good explanation!
The main reason for my confusion was trying to understand the "MCLK_XCORE" route on the MC board (that I picked randomly as my first example to understand this). I didn't see that this particular route is connected to two input pins X0D13 and X1D35. And I was trying to map X1D35 to XS1_PORT_1F which made no sense...
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