xCORE-200 USB library and QSPI cohabitation

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cl-b
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xCORE-200 USB library and QSPI cohabitation

Postby cl-b » Fri Sep 15, 2017 3:17 pm

Hi,

We are starting a new design based on xCORE-200 (with USB phy), and I cannot understand clearly whether it is possible to set both USB connection and a QUAD SPI flash on tile 0 or if it is exclusive ?

Thanks
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mon2
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Postby mon2 » Mon Sep 18, 2017 11:58 am

Hi. From our knowledge, if USB is enabled on tile[0], then QSPI is still available on the same tile as the QSPI pins are not highlighted in the yellow color.

If the background color is white in the port map spreadsheet, then those pins are available for your use. So you should be fine to use QSPI and USB on tile[0].

See this thread and the linked spreadsheet:

viewtopic.php?t=4718

https://www.xmos.com/published/xcore-20 ... es-portmap
cl-b
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Postby cl-b » Mon Sep 18, 2017 2:26 pm

Hi,
Thanks for your answer.
In the spreadsheet, pins X0D04, X0D05, X0D06 and X0D07 are reserved for QSPI but they cannot be used if USB is enabled on this tile. So does it mean that QSPI and USB cannot be used on the same tile ?
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mon2
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Postby mon2 » Mon Sep 18, 2017 4:21 pm

I think I see the point of some confusion.

In the port map spreadsheet, the text background color must be referenced to confirm which port pins are available and which are not available.

Summary: QSPI and USB operate with dedicated port pins and both can be enabled on tile[0].

Take for example tile[0] and USB enabled. USB function will use the dedicated port pins on the device.

With USB enabled on tile[0], the yellow background port pins are no longer available (so P8A0..P8A7, P8B0..P8B7, P16A0..P16A15, P32A20..P32A31 and the highlighted P1Ax pins.

With USB enabled on tile[0], the white background in the spreadsheet port pins P4A, P4B, P4C, P4D are available.

We have confirmed this in the past and posted our results in another thread.

viewtopic.php?f=7&t=3469&p=20173&hilit=Al+xcore+200+port+pins#p20173

Think of the device with assorted internal multiplexers which permits some access but not all to internal ports.

So back to your question, the QSPI port pins (X0D1, X0D04-X0D07, X0D10) should be mapped to your external QSPI capable flash device. Continue to use the USB port pins on your package as shown in the respective datasheet. Be sure to apply the in-rush current protection onto the Vbus rail to prevent CPU damage. We suggest the use of a suitable USB load switch which will do the same and even more (ie. soft start, etc.).

To rephrase the above, during boot time, the fixed (since the boot function is in OTP supplied by XMOS) QSPI port pins will be used to boot your code. After booting, you are technically free to tickle P4B0..P4B4 and the associated port pin on tile[0] will toggle accordingly (ie. X0D04..X0D07). But if you attempt to do the same with P8A0..P8A7 (or P16A0..P16A15 or P32A20..P32A31) then the same port pins will NOT toggle as these alternate port pins and widths are disabled if USB is enabled on this tile[0]. Just take care to not load down these lines with your external hardware else the flash info could be corrupted during boot time.

Hope this is clear.

Update - forgot to include that QSPI requires the use of X0D10 for QSCLK.
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Postby cl-b » Mon Sep 18, 2017 5:02 pm

Many thanks for all these explanations; it is clearer now.
I just have another question regarding this problem : what happens during device firmware update using DFU ? QSPI can be accessed ? Is it possible to write in the QSPI flash data partition ?
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Postby mon2 » Mon Sep 18, 2017 7:39 pm

Yes, the QSPI flash is able to be accessed by your code for data storage. The following thread may be helpful:

viewtopic.php?f=37&t=6002&hilit=how+to+store+data+flash
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Postby cl-b » Wed Sep 20, 2017 10:16 am

Just another question. Is this port mapping valid ?



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mon2
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Postby mon2 » Sat Sep 23, 2017 1:33 pm

Hi. If your question is if you can use X0D16..X0D19 then the answer is yes. However, you will only be able to access this block of port pins as P04D0..P04D3. That is, in a block of 4 pins at a time.

So as an example, if you were to output onto P04D with a value of 0x0f then X0D16..X0D19 should be all "1". The 8B2..8B5 and 16A10..16A13 will not yield any results onto the same port pins as they are in yellow highlight in the port map spreadsheet. You will be "shooting blanks" unless you make use of the P04D port width.

Historically, the XMOS CPU devices will require you to operate such a block of ports all in the same direction (ie. all output or all input) but there is some unique feature on the XCORE-200 series that removes this restriction. Scan this user forum for more details. We have not tested this feature as of this writing where you can turn around individual port bits in a larger block of of ports (ie. some bits to be output while some to be input).

Also, suggest that you post the relevant portions of your pending design for a review. It is vital to get your power supply current draw; power supply sequencing; USB ESD protection; USB in-rush current protection all correct for a working design. Being USB related, be sure to use impedance matched traces for the USB interface -> be sure to highlight these traces so the PCB shop can monitor and comply with the request for your impedance controlled PCB design. The PCB shop must be involved as the final fabrication of the PCB is directly linked to the laminate being used. The shop we often use for our USB designs (Tiefa PCB, Shenzhen, CN), charges +$10 USD for a TDR report using specialized equipment for our design. This report verifies that the PCB was properly produced by the PCB vendor. We have produced a number of USB 2.0 HS and USB 3.1 SS designs with success using these same procedures.

Hope this is clear. Write back if it is not.

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