Since the DRDY signal time is only about 40 ns, and the sampling statement executes about 10 ns per step, the data in the following several channels is misaligned. I would like to know if eight channels can be sampled at the same time.
Code: Select all
//port config:
on tile[0] : clock clk = XS1_CLKBLK_1;
on tile[0] : in port p_clk_in = XS1_PORT_1I;//using external AD CLK
on tile[0] : in port p_rd = XS1_PORT_1J;// DATA READY SIGNAL
on tile[0] : in buffered port:32 chan_1 = XS1_PORT_1L;//DATA CHANNEL
on tile[0] : in buffered port:32 chan_2 = XS1_PORT_1K;
on tile[0] : in buffered port:32 chan_3 = XS1_PORT_1M;
on tile[0] : in buffered port:32 chan_4 = XS1_PORT_1N;
on tile[0] : in buffered port:32 chan_5 = XS1_PORT_1O;
...
//wait for data ready signal which last about 40ns. it's not enough.
select
{
case p_rd when pinsneq(0):> cmd:
//delay_ticks(1);
chan_1:> valdata1[k];
clearbuf(chan_1);
chan_2:> valdata2[k];
clearbuf(chan_2);
chan_3:> valdata3[k];
clearbuf(chan_3);
//here time is not enough for me to capture all data ,so the next channel is wrong.
chan_4:> valdata4[k];
clearbuf(chan_4);
chan_5:> valdata5[k];
clearbuf(chan_5);
k++;
break;//
}
=============Channel 3==================
00010011010000111011010000001110
the channel : 3 , the volt is 2.166507
=============Channel 4==================
00000010000110111111111111101101
the channel : 4 , the volt is 2.166013
00101100100001110101110100001110
the channel : 4 , the volt is 4.213932