How many UARTS will fit in an XMOS chip?

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lslarry86
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How many UARTS will fit in an XMOS chip?

Postby lslarry86 » Wed Apr 11, 2018 1:48 pm

Hi folks. I'm just getting into my first XMOS kit. My application involves at least 5 full duplex UARTS at 115200 N81, plus some I/O, running complex 50 mS cycles. It looks like the UART Library accessible through Eclipse uses a whole core for each direction.

Is there a different UART library that lets me gang 2 or 4 UARTS in one core?

What is the reasonable limit on the number of UARTS if I need, say, 6 I/O points? What if i need Ethernet too?

My current design uses an ARM for Ethernet, talking to 1 or 2 Parallax Propeller chips, each with 5 UARTS active. I'm hoping to consolidate in one XMOS and maybe add a UART or two. Will that work?

Thanks,
Larry
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mon2
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Postby mon2 » Wed Apr 11, 2018 5:13 pm

Hi Larry. Welcome. XMOS is all s/w IP based so the solution is all up to you. However, you will need to define which port pins are input, which are output. Then proceed to group such ports so that the group may work all in the same direction. For example, if you apply a 4 bit port then all 4 bits of that port should be either all input or all output. Just keep that in mind.

What is your max baud rate for this design? 115.2k and under or do you expect to use higher speed?

Here is an appnote that is on topic:

https://www.xmos.com/published/serial-t ... ntation%29

This design is based on the XS1 processors but you should really consider the XCORE-200 (current and enhanced line of CPU devices). For example, the XE216 onboard the XCORE200 Explorer Kit should be able to do it all with a single CPU (has built in Ethernet). Review their Hardware Manual for schematic details. Just apply the external interface 232 or whatever xcvrs.

Since you are talking about standard PC baud rates, you will need to apply an external 1.8432 Mhz clock source (or a multiple of)(as per this appnote) to allow for the UART IP to frame accurately. The default XMOS CPU clock is not accurate for use with the UART IP so an external clock source is used. The 50 ms is not an issue as the XMOS devices. Best to review and mimic the above S2E appnote. The latest XMOS devices are the XCORE-200 series so for your interest, consider to source the XMOS Explorer Kit for the XCORE-200 series. Then apply the code and perform your S2E onto some CMOS level ports. Proceed to add your external RS232 / RS422 or RS485 transceivers with or without isolators to offer a proof of concept. I think the only small hurdle will be to work with an IP that is supported upstream using some off the shelf Windows, etc. software to allow for enumeration of this end product. Then you should be able to have xx virtual com ports on Windows, etc. that can work with this black box.
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infiniteimprobability
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Postby infiniteimprobability » Thu Apr 12, 2018 10:28 am

There is an 8 channel UART library that does 8 channels unidirectional per core: https://github.com/xmos/lib_uart

So using 4 x 8 b ports and 4 cores you could have 16 bi directional UARTs. You could add at least another 4 UARTs using 8 x 1b ports and 4 cores so 20 bi-directional UARTs per tile should be possible..
lslarry86
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Postby lslarry86 » Thu Apr 12, 2018 1:04 pm

Mon2, thank you for your reply. I have ordered the X200 ethernet dev board from Digikey. It will take me a while to digest this information.

What is your max baud rate for this design?


My serial targets top out at 115 kbps. If tat changes, I would want to take advantage of higher baud rates.

In general, does each full duplex UART take up two logical cores, one for TX and one for RX?
lslarry86
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Postby lslarry86 » Thu Apr 12, 2018 1:06 pm

infinite: thanks. I should have refreshed before replying to mon2. I get it now. It's awesome :)

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