Hi, all:
I Use Microphone array library V2.0.0, 16KHz output by default (3.072MHz PDM clock),now I wanna down CLK frequency of PDM to 1.536MHz, as 16KHz output by 1.536MHz PDM CLK.
I tried:
1、configure_clock_src_divide(pdmclk, p_mclk, 2) ——> configure_clock_src_divide(pdmclk, p_mclk, 4);
2、
configure_clock_src_divide(pdmclk, p_mclk, 2) --> configure_clock_src_divide(pdmclk, p_mclk, 3);
and
unsigned decimationfactor = 96000/samplerate-->unsigned decimationfactor = 64000/samplerate;
It's not that simple,doesn't work!
So,please help me! look forward to your reply,THX
How to reduce CLK frequency of PDM Topic is solved
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Good afternoon,
Thank you very much for your enquiry.
Have you reviewed the applications notes (AN218 to 220) that are available here : https://www.xmos.com/support/appnotes.
You might like to try making your additions to one of these app notes.
Best regards,
John
Thank you very much for your enquiry.
Have you reviewed the applications notes (AN218 to 220) that are available here : https://www.xmos.com/support/appnotes.
You might like to try making your additions to one of these app notes.
Best regards,
John
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- Junior Member
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- Joined: Mon Dec 12, 2016 3:31 am
Thx,johned
I'm working on it.
I'm working on it.
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- Junior Member
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- Joined: Mon Dec 12, 2016 3:31 am
Hi, John
I was reviewed the applications notes (AN218 to 220),not found the point about CLK frequency,if I missed something,please let me know.My request is very simple, just wanna down CLK frequency(defualt 3.072) to 1.536(half of it),please check the attachment。
If I missed, please give me the code for direct.
THX!
I was reviewed the applications notes (AN218 to 220),not found the point about CLK frequency,if I missed something,please let me know.My request is very simple, just wanna down CLK frequency(defualt 3.072) to 1.536(half of it),please check the attachment。
If I missed, please give me the code for direct.
THX!
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