How to reduce CLK frequency of PDM
Posted: Mon Dec 12, 2016 4:31 am
Hi, all:
I Use Microphone array library V2.0.0, 16KHz output by default (3.072MHz PDM clock),now I wanna down CLK frequency of PDM to 1.536MHz, as 16KHz output by 1.536MHz PDM CLK.
I tried:
1、configure_clock_src_divide(pdmclk, p_mclk, 2) ——> configure_clock_src_divide(pdmclk, p_mclk, 4);
2、
configure_clock_src_divide(pdmclk, p_mclk, 2) --> configure_clock_src_divide(pdmclk, p_mclk, 3);
and
unsigned decimationfactor = 96000/samplerate-->unsigned decimationfactor = 64000/samplerate;
It's not that simple,doesn't work!
So,please help me! look forward to your reply,THX
I Use Microphone array library V2.0.0, 16KHz output by default (3.072MHz PDM clock),now I wanna down CLK frequency of PDM to 1.536MHz, as 16KHz output by 1.536MHz PDM CLK.
I tried:
1、configure_clock_src_divide(pdmclk, p_mclk, 2) ——> configure_clock_src_divide(pdmclk, p_mclk, 4);
2、
configure_clock_src_divide(pdmclk, p_mclk, 2) --> configure_clock_src_divide(pdmclk, p_mclk, 3);
and
unsigned decimationfactor = 96000/samplerate-->unsigned decimationfactor = 64000/samplerate;
It's not that simple,doesn't work!
So,please help me! look forward to your reply,THX