clocks on xvf3000 reference design

Voice related projects and technical discussions
pisljar
Junior Member
Posts: 6
Joined: Fri Jul 14, 2017 7:19 pm

clocks on xvf3000 reference design

Postby pisljar » Mon Jul 17, 2017 1:39 pm

Hello,

looking at the reference design i have a few questions regarding clocks:
- Si5351A is used to generate 3 clocks:
-- 32K (seems to be used for wifi module ?)
-- 24M for xvf3000
-- 24.576 low jitter master clock used for MCLK_DAC, MCLK_TILE1 and MCLK

it also mentions that clock speeds are docuented in the software manual, but its not available yet, so i am wondering:

- what are the MCLK_TILE1 and MCLK clocks used for ?
- is it possible to omit them (can XVF generate them ? or are they only needed for part of functionality ?)


some additional questions i have:
- how important are the clock buffers ? possible to omit them ?

- whats the FB1 used for ? how important is it and is it possible to omit it ?

- what about NC7WZ07 ? can it be omitted ? can it be replaced with something simpler ?


thanks a lot, looking forward to your reply
User avatar
infiniteimprobability
XCore Expert
Posts: 1006
Joined: Thu May 27, 2010 10:08 am

Postby infiniteimprobability » Wed Jul 19, 2017 11:42 am

- what are the MCLK_TILE1 and MCLK clocks used for ?

MCLK on tile[0] is used to clock a clockblock which then prescales by 8 to provide the PDM clock for the mics. 24.576->3.072MHz
MCLK_TILE1 provides a copy of the master clock for USB audio cases which is used in the explicit feedback calculation for the isochronous endpoints.
It is also used to generate the BCLK and LRCLK in the USB audio case to clock the DAC

- is it possible to omit them (can XVF generate them ? or are they only needed for part of functionality ?)

You need a PDM clock (3.072M) somehow and the on-board DAC needs an MCLK to work properly. You could probably get rid of the connection to tile[1] with some additional effort but I don't think you can delete it altogether.

some additional questions i have:
- how important are the clock buffers ? possible to omit them ?

Maybe, if you had a series resistor per trace and the traces were all matched in length. MUltiple reflections at different times due to unmatched clock tree wouldn't be nice.. This is probably a question more for Silicon Labs than XMOS..

- whats the FB1 used for ? how important is it and is it possible to omit it ?

It's a performance optimisation to reduce noise. If you FFT the output from the mics it's possible to see the switching supply noise (~1.5MHz) so it's there to reduce that influence. Again, probably a question for your PDM mic vendor..

- what about NC7WZ07 ? can it be omitted ? can it be replaced with something simpler ?

The XTAG debug adapter has a push pull drive so something is needed to allow the reset to be shared with POR. If you want to go super-cheap maybe a schottky diode..
User avatar
infiniteimprobability
XCore Expert
Posts: 1006
Joined: Thu May 27, 2010 10:08 am

Postby infiniteimprobability » Wed Jul 19, 2017 12:31 pm

-- 32K (seems to be used for wifi module ?)


Correct - unused in the current reference design
pisljar
Junior Member
Posts: 6
Joined: Fri Jul 14, 2017 7:19 pm

Postby pisljar » Wed Dec 27, 2017 8:21 pm

i have few more questions regarding the clock on evaluation board of XVF3100

Si5351A is used for clock generation ...
- is this chip preprogrammed to output some clocks ? (like 24M ... which is needed in order to flash xmos if i understand correctly ? )
- if so, why is I2C connection to Si5351 needed ? (does xmos need to change clocks during its operation ? or is just one clock -- 24M -- preprogrammed and the other two need to be set over I2C interface ?)

thank you for your help.
User avatar
mon2
XCore Expert
Posts: 1013
Joined: Thu Jun 10, 2010 11:43 am
Contact:

Postby mon2 » Wed Dec 27, 2017 10:28 pm

Hello pisljar. Guessing that you are asking to possible replace this PLL (Si5351A)?

Short answer: Do not remove from the design due to the flexibility of this PLL device. Using the I2C interface any of the 3 output clocks can be changed to suit the project and/or downstream CODEC.

Long answer:

1) See the schematic for your PCB and note the labels on the clock outputs and the p/n Si5351A-B04486.

2) The p/n is a custom assigned suffix label from Silabs and is for XMOS. XMOS defined the desired power up clock output values. When you order from Digikey, this part will power up and output the pre-defined clock outputs.

https://www.silabs.com/internal-apps-ma ... dendum.pdf

https://www.digikey.ca/product-detail/e ... SD&lang=en

The power up clock output values are:

Image

The PCB schematic shows this part as:

Image

Note that CLK2 is listed as 32.768khz so the XMOS IP must be using the I2C interface to alter this power up OTP value from the 45.1584 Mhz to generate 32.768khz for this project.

CLK1 = 24 Mhz for the XMOS CPU clock.

CLK0 = CODEC clocks. Not sure of the exact clock value for this leg of the PLL.

Conclusion: Keep this part in the design for the sanity of this design and to enjoy a power up - "It works!" moment. Note however, that if you hunt down XMOS widgets on Aliexpress, many designers are using fixed clock sources. Really do not see the value of this and believe it is too restrictive. Prefer the PLL idea over fixed clocks.

Disclaimer: Do not own this PCB and the above comments are from reviewing the posted public schematics and reference material from Silabs. We do use the Si5351A in some of our designs and really like this PLL over others we have attempted to deploy. Being that it is not from Cypress, expect the PLL to be in production for a while.
pisljar
Junior Member
Posts: 6
Joined: Fri Jul 14, 2017 7:19 pm

Postby pisljar » Mon Jan 15, 2018 7:00 pm

thank you a lot for your reply, this was very helpful.

to clarify my reasons, i was wondering if connecting Si5351 i2c to my main microcontrolelr (instead of xmos) would be a good idea. however looking at the source code made me think i better leave this as it is.

Who is online

Users browsing this forum: No registered users and 2 guests