SRAM interfacing to XMOS XS1 devices

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vinodkaruvat
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SRAM interfacing to XMOS XS1 devices

Post by vinodkaruvat »

Hello,

I am working on a project wherein I have to design a system wherein I am using the 32 core XS1. Each of the tiles have 256kB SRAM. Now, I am trying to interface additional SRAMs,SDRAMs or even DDR SDRAMs.

For SDRAM, I was going through the forums - http://www.xcore.com/forum/viewtopic.php?f=5&t=105.
It discusses the XShell board and the works on it. The XShell has an SDRAM from Micron. But the link given to the XShell is obsolete. Can I have the link for the said design ? I understand that DDR variants may not be so straight forward as XMOS cannot double clock. So, I will need a glue logic for that interfacing, right ?

Regarding the interfacing of the memory to the XMOS, I believe , the software drivers are available in the Git. Is there any app note explaining the interfacing please ?


Choughtosh
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Post by Choughtosh »

Good morning,

Please consult lib_sdram for details on the SDRAM support.

XMOS SDRAM library

There is also a slice board which implements a SDRAM device. The details are found here :

SDRAM Slice

Note, that due to an error in routing the xCORE200- SliceKits are not suitable for SDRAM evaluation.

DDR is not straight forward, due to the double data rate and there is no factory supported implementation. If you are going to attempt this, you should observe the maximum IO rate (T(XIFMAX)) in the datasheet.

Thanks,

Rob
colin
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Post by colin »

Hi,

Please find attached the xshell project you were looking for.

Colin
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vinodkaruvat
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Post by vinodkaruvat »

Hello ,

Thank you for the responses. Along with this SDRAM, I wanted to know how can I interface an external flash as well to the XMOS devices (especially the 32 core, flash ones). In other words increase the flash (program memory) of the system.
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infiniteimprobability
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Post by infiniteimprobability »

Thank you for the responses. Along with this SDRAM, I wanted to know how can I interface an external flash as well to the XMOS devices (especially the 32 core, flash ones). In other words increase the flash (program memory) of the system.
You cannot execute out of external flash - there is no external data bus. It needs to be loaded into on-chip SRAM first (hence device boot sequence). The tools do support code overlays which can allow you to have a program bigger than SRAM

https://www.xmos.com/download/private/R ... s(1.0).pdf

..but it's a bit clunky to use and debug, and there is a run time hit when you get an overlay miss and the code needs brining in from flash. Anything real-time should not use this mechanism.
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