again "Cannot load image, XCore 0 is not enabled"

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revenac
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again "Cannot load image, XCore 0 is not enabled"

Postby revenac » Mon Apr 10, 2017 4:15 pm

Hello all,
I am new with the XMOS processors, and I am facing a trouble to do the first steps.
I have a decent knowledge with "classic" microprocessors like, for example, Atmega 1284P.
I have worked with them since many year, hardware, firmware ... whatever.

I familiarized with XMOS playing with the xCORE-200 eXplorerKIT + xTAG.
Everything is fine. The eXplorerKIT arrived already programmed and I started from an already working platform.

After the setup of my solution and explored with the xCORE-200 I prepared my board where simply I cut the functions of the eXploreKIT not needed in my application.
Basically XU216-256-TQ128 instead of the XEF216-512-TQ128.
IS25LQ080 QSPI instead of IS25LQ080B because I have a lot already (used in another production).

When I try to flash the QSPI, a IS25LQ080 (without the B at the end), I receive from XTcomposer the "well-known" & frustrating message "Cannot load image, XCore 0 is not enabled".

Studied as deeply as possible the online documentation and the replies on xmos.com and xcore.com; understood that the XU216 is not running.

xTAG works properly with the eXploreKIT, can flash and the applications works, so it not dead.
I double checked the RST_N signal, the power-on sequence, the presence of the CLK.
VDD is 1.00V, VDDIO is 3.32V, PLL resistor is 4R7.
IS25LQ080 is very close to the IS25LQ080B and the JDEC ID is the same.
I have compared with the same things on the eXploreKIT.
Almost the same, and within the specifications of the data sheet.

Two things I cannot say if are OK or not:
1) "The JTAG interface to the XCore has been disabled in the OTP security register"
do have I to initialize the OTP before to flush the QSPI?
... how is possible to access the OTP security register?
This One-Time Programmable register can be ruined ... with a wrong setup for example? I mean, if ruined is possible to configure as needed?
Unfortunately I am conditioned from the Atmega and Microchip structures and I am looking for something close to the "Fuses" and "Flags" you program before to flash the units.

2) "the ground paddle on the bottom of the chip is not well soldered"
I have 3 vias, one with 1mm hole (see attachment) and I am quite confident the pad on the bottom is welded to GND.
With flux, lead, and IR welding machine the pad is for sure soldered.
I cannot distribute the vias regularly, 9 for example as suggested in the data sheet, because I need the space on the other face.


Any suggestion?
How to go back from this dead end?


I have already planned the design of a new board with the vias for the bottom pad distributed as per the data sheet, with also the same suggested size.
But I scare the trouble is because, somewhere, I am missing some basic setup in XTcomposer.


Thank you for any suggestion.
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Postby mon2 » Mon Apr 10, 2017 9:38 pm

Hi. Not sure about the OTP but can you post the relevant schematic for a review ? Also, confirm step 7 of the following:

viewtopic.php?t=3713

which is basically to validate that the power sequencing is correct.

Can you run any code on your custom board ? Start with a simple LED blinky on your custom board. Do not worry about programming the QSPI at this time. Also, to use QSPI, did you define the required XN file ? You can borrow this from the Explorer Kit XN file.

The time between the power rail sequencing is also important to properly bring up this processor.
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Postby revenac » Tue Apr 11, 2017 8:00 am

unfortunately for me the power on sequence seems OK.
I compared with the same in the DevKit.
Pictures of both boards attached.

The XMOS chip doesn't wakeup. So I cannot do nothing.
Why it doesn't wake up keep me not sleeping.

I do not understand where is the trouble and where I have to investigate.
Image

Image

Image

Image
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Postby infiniteimprobability » Tue Apr 11, 2017 9:25 am

1) "The JTAG interface to the XCore has been disabled in the OTP security register"
do have I to initialize the OTP before to flush the QSPI?
... how is possible to access the OTP security register?

I think this is a red herring. Unless you have specifically used xburn then the OTP will be blank. You do not need to do anything with the OTP to get QSPI or any other normal booting to work.

The error message indeed means the xcore is not running, but the JTAG TAP controller is. So you have some parts of the chip working but the core is not seeing all of it's essential life support - power/reset/clock.

We see this error message frequently on custom hardware where something is missing - I can guarantee it will be one of the basics. Are you 100% sure that every point in the datasheet I Schematics Design Check List / J PCB Layout Design Check List is ticked off?

The 3v3/1v0 sequencing looks OK. The reset should be fine too "The RST_N and TRST_N pins are asserted (low) during or after power up". Next thing isb checking valid clock and PLL_AVDD
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Postby infiniteimprobability » Tue Apr 11, 2017 9:28 am

Actually one other point. I see in the datasheet that it says:

"The RST_N and TRST_N pins are asserted (low) during or after power up."

but also:

"RST_N and must be asserted low during and after power up for 100 ns."


Could you try asserting RST during power up too?
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Postby mon2 » Tue Apr 11, 2017 12:23 pm

Agree with infiniteimprobability. The #RST line should be LOW during power up and remain LOW till the last power rail, 1v0 is deemed to be stable. Then the reset supervisor is to release this pin which is usually open drain (so a pull-up to 3v3 is required) to release the #RST line. It appears you have a circuit which is HIGH during power up, then pulsed LOW to a HIGH after 1v0 is stable.

Can you apply a wired LOW onto #RST and then power up ? Then remove the wired LOW to check the results. Hoping your #RST circuit is not push-pull but rather OD (open drain) style.

If available, please post your circuit related to the XMOS CPU, power supply and reset supervisor for a review.
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Postby revenac » Tue Apr 11, 2017 3:13 pm

Image

FAN2558 activates PG when 3V3 is almost 3V1 and stable.
LMZ10501 generates 1V0 but starts when PG is applied.
NCP301 has a thresold of 0.9V, it is OD, and generated one 200uS pulse after 100uS 0.9V are detected.
NC7WZ07 is a double buffer, it buffers the pulse generated by the NCP301 or the pulse arrived from jTAG.

In the shot attached again there is the RST pulse on the upper trace and the 1V0 in the below trace.
Image

I generate a RST of 200uS and not 100nS like in the data sheet, this is the big discrepancy. 20 times larger.
Can it do the difference.

I can apply a RSTbefore power up ??? .... not clear the meaning. if the unit is off anything you do has effect.
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Postby revenac » Tue Apr 11, 2017 3:32 pm

the clock is 24MHz and it run. It is one of the first things I cheked.

... about the PLL_AVDD:
I derive the 3V3 from VDD (exatly the two pins before, #101 & #102).
I filter before to enter PLL_AVDD with 4R7 and 1u. All components are 0402.
So everything is done in the area of 2.5x2millimiters attached to the pin #101 102 103 and 104.
Image
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Postby revenac » Tue Apr 11, 2017 3:44 pm

again about the RST sequency.

I apply 5V from an USB connector to the 3V3 IC and to the 1V0 IC. Diretcly, only 120 uF cap before the 2 IC.
The 1V0 IC stays LOW till 3V3 isn't arrived at 3V1.

When it arrives at 3V1, the 1V0 goes ON (0.9V).

The RST circuit pushes the RST pin HIGH when powered with 3V3, so before 1V0 goes ON.
When 1V0 reaches 0.9V the Reset IC generates a LOW pulse of 200uS.

200uSec and not 100nSec. Problem with this?
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Postby mon2 » Tue Apr 11, 2017 4:23 pm

To be clear, you have 120uf on the VBUS rail from the USB connector ? If yes, that is a violation of the USB spec. Max capacitance that is permitted on VBUS line is 10uf.

The #RST line should remain LOW upon power up and only get released to the 3v3 via PU by the 1v0 PG. Can you test this idea by pressing your PB while powering up and release the PB after a second or so. This will emulate the required sequencing for the #RST line.

What are the results ?

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