FIFO Reclock for i2s on input needed?

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JensH
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FIFO Reclock for i2s on input needed?

Postby JensH » Sun Mar 25, 2018 4:13 pm

Hello,

I use the xu216 as an i2s-usb bridge. 8ch i2s in, 10ch i2s out. An external board is connected to the input of the XMOS Board with BCLK/LRCLK/DATA. I assume the oscillators from the external board are not the best.

What I want to do now is using the XMOS as a slave and use the superior oscillators from the XMOS Boards, 22.5792 mhz or 24.5760 mhz depending on LRCLK. Do I need to reclock the BCLK/LRCLK/DATA before going to the XMOS Board, to archieve lower jitter (For example with an FIFO FLip Flop). Or does the XMOS chip do the reclocking?

Kind Regards
Jens
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infiniteimprobability
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Postby infiniteimprobability » Tue Mar 27, 2018 11:13 am

Can you explain the clock architecture of the other board and state which I2S roles each side should be (which is master/slave). From what you have written, it sounds like both may want to be clock master? This is not possible unless you have ASRC which is a lot of extra work + resources.
JensH
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Postby JensH » Tue May 22, 2018 7:05 am

Hello,

I have an DSP which receives a stereo SPDIF Stream. It gives out an 6ch i2s stream.

The xmos board is in slave mode ,so is the DAC. The clocks are recovered by the DSP from the SPDIF. The Problem is now,that I don't want to drive the xmos and the DAC attached to the xmos with the inferior jittery clocks from the spdif.

I think there are ways with an FIFO, so that I can just take only the samples from the i2s stream but not the clock, and use new low jitter clocks which are driving the xmos and dac.

Regards
Jens
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infiniteimprobability
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Postby infiniteimprobability » Wed May 23, 2018 4:27 pm

OK, so your DSP receives SPDIF and provides an I2S master. Does it also provide MCLK?

The xmos designed needs MCLK input, even when it is slave, to be able to work out the explicit feedback value reported to the USB host.

So, as I understand it, you want to *not* use the clocks from the DSP because they are too jittery. In that case you have two options:

- Use a PLL to clean up the clock from the DSP. Although it would only be the DAC that cares about this (perhaps use a DAC with built in PLL?) because the jitter will not make it through to the USB host
- Use ASRC so that the I2S->USB bridge has it's own local free-running clock (which can be as good as you can afford) which is asynchronous to the DSP clock

Option 1) means board/component cost
Options 2) means software development cost, although the IP (lib_src) is free. This is certainly weeks of SW development by the time.
JensH
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Postby JensH » Fri May 25, 2018 6:07 pm

Hello and thank you for your detailed answer :)

I think I will use an hardware ASRC such as the TI src4192. I Think this will give me much more flexibility and a secure usb interface, also I can use the usb host as playbak hardware, what is IMO the best solution in term of audio quality/jitter.
Furthermore, I think the DSP has no MCLK, so the solution with the ASRC is not an alternative, it's a need.

By the way, I returned my custom board to my vendor and decided to design my own board, in order to have more flexibility and the option to completely embed the XMOS chip in my design. And now the question arises, whether to chose the XUF216, or a bigger version of the chip. I need at least 6 channels input, maybe 8 channels but I think I can use a switch for source selection, so 6channels should be sufficient. And at least 10 channels out, the more the better; for future projects. What do you think? Do you think there are enough 1 Bit ports on the XUF216?

Regards and thank You
Jens

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